Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources...Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design au-tomation (EDA) tools, the deviation between our method and HSPICE is under 10% .展开更多
As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on ...As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on account of Krylov subspace techniques. The interpolation points are selected by Haar wavelet using weighted self-adaptive threshold methods dynamically. Through the analyses of different types of circuits in very large scale integration( VLSI),the results show that the method proposed in this paper can be more accurate and efficient than Krylov subspace method of multi-shift expansion point using Haar wavelet that are no weighted self-adaptive threshold application in interest frequency range,and more accurate than Krylov subspace method of multi-shift expansion point based on the uniform interpolation point.展开更多
信号完整性在某种程度上已经成为了限制当前高速电子系统设计与发展的瓶颈。建立了由过孔、焊点、印制线构成的高速电路板复杂互连结构单元模型,在1~10 GHz频率范围内针对模型进行信号传输性能的研究。用高频结构仿真器（HFSS）针对不...信号完整性在某种程度上已经成为了限制当前高速电子系统设计与发展的瓶颈。建立了由过孔、焊点、印制线构成的高速电路板复杂互连结构单元模型,在1~10 GHz频率范围内针对模型进行信号传输性能的研究。用高频结构仿真器（HFSS）针对不连续区域内印制线不同长度、焊盘不同半径进行仿真分析,总结这些参数对信号传输性能的影响,提出了复杂互连结构的等效电路模型,并提取参数值进行对比验证。结果表明,随着印制线长度的增加、焊盘半径的增加,信号传输的回波损耗（RL）越来越强。用先进设计系统（ADS）软件对等效电路进行模拟,其回波损耗在1~6 GHz频率范围内与HFSS仿真结果相差不超过1 d B,在6~10 GHz频率范围内相差不超过2 d B。展开更多
We develop an interconnect crosstalk estimation model on the assumption of linearity for CMOS device. First, we analyze the terminal response of RC model on the worst condition from theS field to the time domain. The ...We develop an interconnect crosstalk estimation model on the assumption of linearity for CMOS device. First, we analyze the terminal response of RC model on the worst condition from theS field to the time domain. The exact 3 order coefficients inS field are obtained due to the interconnect tree model. Based on this, a crosstalk peak estimation formula is presented. Unlike other crosstalk equations in the literature, this formula is only used coupled capacitance and grand capacitance as parameter. Experimental results show that, compared with the SPICE results, the estimation formulae are simple and accurate. So the model is expected to be used in such fields as layout-driven logic and high level synthesis, performance-driven floorplanning and interconnect planning.展开更多
基金This work was supported in part by the National Natural Science Foundation of China (Grant Nos. 69973027 and 60025101)by the National Fundamental Basic Research Program (973) (Grant No. G1999032903).
文摘Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design au-tomation (EDA) tools, the deviation between our method and HSPICE is under 10% .
基金Sponsored by the Fundamental Research Funds for the Central Universities(Grant No.HIT.NSRIF.2016107)the China Postdoctoral Science Foundation(Grant No.2015M581447)
文摘As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on account of Krylov subspace techniques. The interpolation points are selected by Haar wavelet using weighted self-adaptive threshold methods dynamically. Through the analyses of different types of circuits in very large scale integration( VLSI),the results show that the method proposed in this paper can be more accurate and efficient than Krylov subspace method of multi-shift expansion point using Haar wavelet that are no weighted self-adaptive threshold application in interest frequency range,and more accurate than Krylov subspace method of multi-shift expansion point based on the uniform interpolation point.
文摘信号完整性在某种程度上已经成为了限制当前高速电子系统设计与发展的瓶颈。建立了由过孔、焊点、印制线构成的高速电路板复杂互连结构单元模型,在1~10 GHz频率范围内针对模型进行信号传输性能的研究。用高频结构仿真器（HFSS）针对不连续区域内印制线不同长度、焊盘不同半径进行仿真分析,总结这些参数对信号传输性能的影响,提出了复杂互连结构的等效电路模型,并提取参数值进行对比验证。结果表明,随着印制线长度的增加、焊盘半径的增加,信号传输的回波损耗（RL）越来越强。用先进设计系统（ADS）软件对等效电路进行模拟,其回波损耗在1~6 GHz频率范围内与HFSS仿真结果相差不超过1 d B,在6~10 GHz频率范围内相差不超过2 d B。
基金SupportedbytheNationalHighTechnologyResearchandDevelopmentProgramofChina (863Plan) (863 SOC Y 3 3 2 )
文摘We develop an interconnect crosstalk estimation model on the assumption of linearity for CMOS device. First, we analyze the terminal response of RC model on the worst condition from theS field to the time domain. The exact 3 order coefficients inS field are obtained due to the interconnect tree model. Based on this, a crosstalk peak estimation formula is presented. Unlike other crosstalk equations in the literature, this formula is only used coupled capacitance and grand capacitance as parameter. Experimental results show that, compared with the SPICE results, the estimation formulae are simple and accurate. So the model is expected to be used in such fields as layout-driven logic and high level synthesis, performance-driven floorplanning and interconnect planning.
