分布式拒绝攻击(distributed denial of service,DDoS)作为一种传统的网络攻击方式,依旧对网络安全存在着较大的威胁.本文研究基于高性能网络安全芯片SoC+IP的构建模式,针对网络层DDoS攻击,提出了一种从硬件层面实现的DDoS攻击识别方法...分布式拒绝攻击(distributed denial of service,DDoS)作为一种传统的网络攻击方式,依旧对网络安全存在着较大的威胁.本文研究基于高性能网络安全芯片SoC+IP的构建模式,针对网络层DDoS攻击,提出了一种从硬件层面实现的DDoS攻击识别方法.根据硬件协议栈设计原理,利用逻辑电路门处理网络数据包进行拆解分析,随后对拆解后的信息进行攻击判定,将认定为攻击的数据包信息记录在攻击池中,等待主机随时读取.并通过硬件逻辑电路实现了基于该方法的DDoS攻击识别IP核(intellectual property core),IP核采用AHB总线配置寄存器的方式进行控制.在基于SV/UVM的仿真验证平台进行综合和功能性测试.实验表明,IP核满足设计要求,可实时进行DDoS攻击识别检测,有效提高高性能网络安全芯片的安全防护功能.展开更多
In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design...In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.展开更多
基于可编程门阵列(FPGA)设计JTAG(joint test action group)控制器知识产权(IP)软核,可以实现在线测试.通过分析测试访问端口(TAP)控制器状态机及边界扫描专用控制器芯片原理,针对发动机控制器中常用的数字信号处理器(DSP)芯片,设计了J...基于可编程门阵列(FPGA)设计JTAG(joint test action group)控制器知识产权(IP)软核,可以实现在线测试.通过分析测试访问端口(TAP)控制器状态机及边界扫描专用控制器芯片原理,针对发动机控制器中常用的数字信号处理器(DSP)芯片,设计了JTAG控制器IP软核以及基于该IP软核的边界扫描测试验证系统的硬件电路,完成了主要指令的测试.采用该IP软核可以灵活地加载扫描矢量,实现在线测试.该设计可以用于扫描测试、故障注入等多个领域.展开更多
文摘基于IP核的技术设计了一种快速数字电平转换电路.采用电压-电流-电压的方式实现不同电压域的电平转换,引入单稳态延时电路和快慢速通道提高电平转换速度和降低静态功耗,并给出了与标准CMOS工艺兼容的扩展漏极高压MOS管的优化设计.仿真结果表明:在将-5^+5 V电压域的数字电平转换成0^+12V的电压域时,其延时可低于10 ns.
基金Project supported by the IC Special Foundation of Shanghai Municipal Commission of Science and Technology (Grant No.09706201300)the Shanghai Municipal Commission of Economic and Information (Grant No.090344)the Shanghai High-Tech Industrialization of New Energy Vehicles (Grant No.09625029),and the Graduate Innovation Foundation of Shanghai University
文摘In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.
文摘基于可编程门阵列(FPGA)设计JTAG(joint test action group)控制器知识产权(IP)软核,可以实现在线测试.通过分析测试访问端口(TAP)控制器状态机及边界扫描专用控制器芯片原理,针对发动机控制器中常用的数字信号处理器(DSP)芯片,设计了JTAG控制器IP软核以及基于该IP软核的边界扫描测试验证系统的硬件电路,完成了主要指令的测试.采用该IP软核可以灵活地加载扫描矢量,实现在线测试.该设计可以用于扫描测试、故障注入等多个领域.
