摘要
SoC设计很大程度上依赖于IP核的可重用性。由于各IP核中时钟延时的不同,要将IP核集成到一个同步SoC中时钟分布变得很难。本文介绍了一种SoC时钟同步设计方法,这种方法将可调节延时的时钟电路插入在时钟分布网络中,以取得时钟边沿的匹配和同步。使用可调节电路进行时序调整,减少了设计迭代时间,节约了设计成本。
System-on-Chip （SoC） design depends heavily on effective reuse of semiconductor Intellectual Property （IP）. Clock distribution has become a problem for integrating IP cores into a single synchronous SoC, because of different clock delays in the IP cores. We introduce an on-chip clock synchronous method, in which programmable delays are inserted in the clock distribution network, such that clock alignment and synchronization are achieved. Design iterations are eliminated with the use of the tuninz circuit, savinz design effort and cost.
出处
《微电子学与计算机》
CSCD
北大核心
2005年第9期170-172,共3页
Microelectronics & Computer
关键词
时钟分布
延时插入
调整电路
IP核
SOC
Clock distribution, Inserted delay, Circuit tuning, Intellectual Property （IP） core, System-on-Chip （SoC）.
