Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors （p-MOSFETs） with hafnium silicon oxynitride （HfSiON） gate dielectric and tantalum nitride （TAN） metal gate are fabricated. Self-isolated rin...Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors （p-MOSFETs） with hafnium silicon oxynitride （HfSiON） gate dielectric and tantalum nitride （TAN） metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor （MOS） capacitors may be caused by charge trapping centres in GeOx （1 〈 x 〈 2）. Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/（V.s） and 81.0 cm2/（V.s）, respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.展开更多
针对大面积碲镉汞表面钝化膜的应力问题,基于磁控溅射技术在3 in Ge基碲镉汞表面采用不同工艺条件沉积了ZnS钝化膜,并对其进行了退火处理。利用台阶仪和原子力显微镜(AFM)对ZnS钝化膜的应力及表面形貌进行了表征分析,结果表明:在磁控溅...针对大面积碲镉汞表面钝化膜的应力问题,基于磁控溅射技术在3 in Ge基碲镉汞表面采用不同工艺条件沉积了ZnS钝化膜,并对其进行了退火处理。利用台阶仪和原子力显微镜(AFM)对ZnS钝化膜的应力及表面形貌进行了表征分析,结果表明:在磁控溅射方法中适当提高沉积温度和降低溅射功率,有效降低了ZnS钝化膜应力,平均应力由原来的924 MPa减小到749 MPa,且提高了应力分布均匀性;此外,退火处理有效降低了钝化膜的应力,并改善了ZnS薄膜的晶粒大小一致性和致密度。该研究为减小大尺寸碲镉汞表面钝化膜应力提供了思路。展开更多
Molecular beam epitaxy growth of an In;Ga;As/GaAs quantum well（QW） structure（x equals to 0.17 or 0.3） on offcut（100） Ge substrate has been investigated.The samples were characterized by atomic force microscopy,p...Molecular beam epitaxy growth of an In;Ga;As/GaAs quantum well（QW） structure（x equals to 0.17 or 0.3） on offcut（100） Ge substrate has been investigated.The samples were characterized by atomic force microscopy,photoluminescence（PL）,and high resolution transmission electron microscopy.High temperature annealing of the Ge substrate is necessary to grow GaAs buffer layer without anti-phase domains.During the subsequent growth of the GaAs buffer layer and an In;Ga;As/GaAs QW structure,temperature plays a key role. The mechanism by which temperature influences the material quality is discussed.High quality In;Ga;As/GaAs QW structure samples on Ge substrate with high PL intensity,narrow PL linewidth and flat surface morphology have been achieved by optimizing growth temperatures.Our results show promising device applications forⅢ-Ⅴcompound semiconductor materials grown on Ge substrates.展开更多
This paper describes a method using both reduced pressure chemical vapor deposition （RPCVD） and ultrahigh vacuum chemical vapor deposition （UHVCVD） to grow a thin compressively strained Ge film. As the first step,...This paper describes a method using both reduced pressure chemical vapor deposition （RPCVD） and ultrahigh vacuum chemical vapor deposition （UHVCVD） to grow a thin compressively strained Ge film. As the first step, low temperature RPCVD was used to grow a fully relaxed SiGe virtual substrate layer at 500 ℃ with a thickness of 135 nm, surface roughness of 0.3 nm, and Ge content of 77%. Then, low temperature UHVCVD was used to grow a high quality strained pure Ge film on the SiGe virtual substrate at 300 ℃ with a thickness of 9 nm, surface roughness of 0.4 nm, and threading dislocation density of - 10^5 cm^-2. Finally, a very thin strained Si layer of 1.5-2 nm thickness was grown on the Ge layer at 550 ℃ for the purpose of passivation and protection. The whole epitaxial layer thickness is less than 150 nm. Due to the low growth temperature, the two-dimensional layer-by-layer growth mode dominates during the epitaxial process, which is a key factor for the growth of high quality strained Ge films.展开更多
基金supported by special funds for major state basic research project(2011CB301900)hi-tech research project (2009AA03A198)+2 种基金national nature science foundation of China(60990311,60721063,60906025,60936004)The nature science foundation of Jiangsu province(BK2008019,BK2009255,BK2010178)the researchfunds from NJU-Yangzhou Institute of Opto-electronics
基金Project supported by the National Basic Research Program of China (Grant No. 2006CB302704)
文摘Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors （p-MOSFETs） with hafnium silicon oxynitride （HfSiON） gate dielectric and tantalum nitride （TAN） metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor （MOS） capacitors may be caused by charge trapping centres in GeOx （1 〈 x 〈 2）. Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/（V.s） and 81.0 cm2/（V.s）, respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.
文摘针对大面积碲镉汞表面钝化膜的应力问题,基于磁控溅射技术在3 in Ge基碲镉汞表面采用不同工艺条件沉积了ZnS钝化膜,并对其进行了退火处理。利用台阶仪和原子力显微镜(AFM)对ZnS钝化膜的应力及表面形貌进行了表征分析,结果表明:在磁控溅射方法中适当提高沉积温度和降低溅射功率,有效降低了ZnS钝化膜应力,平均应力由原来的924 MPa减小到749 MPa,且提高了应力分布均匀性;此外,退火处理有效降低了钝化膜的应力,并改善了ZnS薄膜的晶粒大小一致性和致密度。该研究为减小大尺寸碲镉汞表面钝化膜应力提供了思路。
基金Project supported by the National Natural Science Foundation of China(No60625405)the National Basic Research Program of China (Nos2007CB936304,2010CB327601)
文摘Molecular beam epitaxy growth of an In;Ga;As/GaAs quantum well（QW） structure（x equals to 0.17 or 0.3） on offcut（100） Ge substrate has been investigated.The samples were characterized by atomic force microscopy,photoluminescence（PL）,and high resolution transmission electron microscopy.High temperature annealing of the Ge substrate is necessary to grow GaAs buffer layer without anti-phase domains.During the subsequent growth of the GaAs buffer layer and an In;Ga;As/GaAs QW structure,temperature plays a key role. The mechanism by which temperature influences the material quality is discussed.High quality In;Ga;As/GaAs QW structure samples on Ge substrate with high PL intensity,narrow PL linewidth and flat surface morphology have been achieved by optimizing growth temperatures.Our results show promising device applications forⅢ-Ⅴcompound semiconductor materials grown on Ge substrates.
基金Project supported by the National Natural Science Foundation of China(Nos.60636010,60820106001)
文摘This paper describes a method using both reduced pressure chemical vapor deposition （RPCVD） and ultrahigh vacuum chemical vapor deposition （UHVCVD） to grow a thin compressively strained Ge film. As the first step, low temperature RPCVD was used to grow a fully relaxed SiGe virtual substrate layer at 500 ℃ with a thickness of 135 nm, surface roughness of 0.3 nm, and Ge content of 77%. Then, low temperature UHVCVD was used to grow a high quality strained pure Ge film on the SiGe virtual substrate at 300 ℃ with a thickness of 9 nm, surface roughness of 0.4 nm, and threading dislocation density of - 10^5 cm^-2. Finally, a very thin strained Si layer of 1.5-2 nm thickness was grown on the Ge layer at 550 ℃ for the purpose of passivation and protection. The whole epitaxial layer thickness is less than 150 nm. Due to the low growth temperature, the two-dimensional layer-by-layer growth mode dominates during the epitaxial process, which is a key factor for the growth of high quality strained Ge films.
