A novel scalable model of substrate components for deep n-well (DNW) RF MOSFETs with different number of fingers is presented for the first time. The test structure developed in [1] is employed to directly access the ...A novel scalable model of substrate components for deep n-well (DNW) RF MOSFETs with different number of fingers is presented for the first time. The test structure developed in [1] is employed to directly access the characteristics of the substrate to extract the different substrate components. A methodology is developed to directly extract the parameters for the substrate network from the measured data. By using the measured two-port data of a set of nMOSFETs with different number of fingers, with the DNW in grounded and float configuration, respectively, the parameters of the scalable substrate model are obtained. The method and the substrate model are further verified and validated by matching the measured and simulated output admittances. Excellent agreement up to 40 GHz for configurations in common-source has been achieved.展开更多
A 0.5 V static master-slave D flip-flop （DFF） divider-by-2 is implemented with a 0.13 μm 1P8M RF- mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in ...A 0.5 V static master-slave D flip-flop （DFF） divider-by-2 is implemented with a 0.13 μm 1P8M RF- mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in the circuit. Each of the D-latch with source coupled logic consists of sensing and latching circuits. To increase the maximum operating frequency and decrease power consumption, the latching current is one half of the sensing current. The circuit optimization methods are described in this paper. The measured maximum operating frequency is 6.5 GHz and the minimum input singled-signal amplitude is 0.15 V.展开更多
文摘A novel scalable model of substrate components for deep n-well (DNW) RF MOSFETs with different number of fingers is presented for the first time. The test structure developed in [1] is employed to directly access the characteristics of the substrate to extract the different substrate components. A methodology is developed to directly extract the parameters for the substrate network from the measured data. By using the measured two-port data of a set of nMOSFETs with different number of fingers, with the DNW in grounded and float configuration, respectively, the parameters of the scalable substrate model are obtained. The method and the substrate model are further verified and validated by matching the measured and simulated output admittances. Excellent agreement up to 40 GHz for configurations in common-source has been achieved.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z2A7)the Special Fund of Jiangsu Province for the Transformation of Scientific and Technological Achievements(No.BA2010073)
文摘A 0.5 V static master-slave D flip-flop （DFF） divider-by-2 is implemented with a 0.13 μm 1P8M RF- mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in the circuit. Each of the D-latch with source coupled logic consists of sensing and latching circuits. To increase the maximum operating frequency and decrease power consumption, the latching current is one half of the sensing current. The circuit optimization methods are described in this paper. The measured maximum operating frequency is 6.5 GHz and the minimum input singled-signal amplitude is 0.15 V.
