摘要
低压5 V/高压40 V制程广泛应用于LCD栅驱动芯片,LED驱动芯片,智能电表芯片及电源管理等产品的生产。N型埋层(NBL)加上P型外延层(P-EPI)做隔离的工艺制程已经稳定量产多年,而以深N阱代替NBL+P-EPI的工艺,不需要昂贵的EPI,同时可减少零层光刻(Zero layer),生产成本大幅降低。DNW工艺可以沿用EPI工艺的Layout设计规则,保持了EPI工艺器件的电特性,特别是高压器件的击穿电压(BV)足够满足各种对栅和漏端均需耐40V高压产品的应用需求。
LV 5 V/HV 40 V High voltage process was used to manufacture the chips of LCD gate driver, LED driver,intelligent ammeter, power management and so on. Patterned N type layer be buried under P type EPI as the isolation technology has been mass production for many years. Now we set up Deep N well to replace NBL＋EPI as the isolation and delete Zero mark layer, which will reduce product cost and process cycle. The process with DNW shares the same layout design rule with that with NBL＋EPI. Devices electric parameters especially Breakdown voltage（BV） of HV device are comparable to EPI process. The process with DNW is ready for 40 V high voltage products.
作者
熊淑平
吴长明
XIONG Shuping;WU Changming(Huahong Grace Semiconductor Manufacture Co.,Ltd,Shanghai 201203,China.)
出处
《集成电路应用》
2018年第5期47-51,共5页
Application of IC
基金
上海市软件和集成电路产业发展专项基金(2015.150223)
关键词
集成电路制造
深N阱
NBL
击穿电压
高能注入
高温推进
零层光刻
光刻对位
IC manufacturing
deep N well
NBL
breakdown voltage
high energy injection
high temperature propulsion
zero layer photolithography
lithography alignment
