Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact eq...Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.展开更多
In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is bu...In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.展开更多
Energy harvesting technologies provide a promising alternative to battery-powered systems and create an opportunity to achieve sustainable computing for the exploitation of ambient energy sources. However, energy harv...Energy harvesting technologies provide a promising alternative to battery-powered systems and create an opportunity to achieve sustainable computing for the exploitation of ambient energy sources. However, energy harvesting devices and power generators encompass a number of non-classical system behaviors or characteristics, such as delivering nondeterministic power density, and these would create hindrance for effectively utilizing the harvested energy. Previously, we have investigated new design methods and tools that are used to enable power adaptive computing and, particularly, catering non-deterministic voltage, which can efficiently utilize ambient energy sources. Also, we developed a co-optimization approach to maximize the computational efficiency from the harvested ambient energy. This paper will provide a review of these methods. Emerging technologies, such as 3D-IC, which would also enable new paradigm of green and high-performance computing, will be also discussed.展开更多
基金supported by the National Natural Science Foundation of China(Nos.61234002,61006028,61204044)the National High-Tech Program of China(Nos.2012AA012302,2013AA011203)
文摘Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.
基金The National Natural Science Foundation of China(No.61674048,61574052,61474036,61371025)the Project of Anhui Institute of Economics and Management(No.YJKT1417T01)
文摘In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.
基金supported by the National Natural Science Foundation of China under Grant No. 61176025 and No. 61006027
文摘Energy harvesting technologies provide a promising alternative to battery-powered systems and create an opportunity to achieve sustainable computing for the exploitation of ambient energy sources. However, energy harvesting devices and power generators encompass a number of non-classical system behaviors or characteristics, such as delivering nondeterministic power density, and these would create hindrance for effectively utilizing the harvested energy. Previously, we have investigated new design methods and tools that are used to enable power adaptive computing and, particularly, catering non-deterministic voltage, which can efficiently utilize ambient energy sources. Also, we developed a co-optimization approach to maximize the computational efficiency from the harvested ambient energy. This paper will provide a review of these methods. Emerging technologies, such as 3D-IC, which would also enable new paradigm of green and high-performance computing, will be also discussed.
