5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm...5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm logic photo process,the most appropriate layers for the EUV lithography are the cut layers,metal layers,and via layers.Generally speaking,critical structures in a lithography process are semi-dense patterns,also known as the“forbidden pitch”patterns,the array edge structures,tip-to-tip structures,tip-to-line structures(under 2D design rules),the minimum area structures,the bi-lines,tri-lines,…,etc.Compared to that from the 193 nm immersion process,the behaviors for the above structures are different.For example,in the 193 nm immersion process,the minimum area is about 2~3 times that of minimum pixel squared,while in EUV photolithographic process,the minimum achievable area is found to be significantly larger.In the simulation,we have kept aware of the stochastics impact due to drastically reduced number of photons absorbed compared to the DUV process,the criteria used for various structures of image contrast are tightened.For example,in 193 nm immersion lithography,we have usually set the minimum Exposure Latitude(EL)for the poly layer,the metal layer,and tip-to-tip pattern,respectively,at 18%,13%,and 10%.However,in EUV lithography,reasonable targets for the minima are,respectively,>18%,18%,and 13%.We have also studied the aberration and shadowing impact to the above design rule structures.We will present the results of our work and our explanations.展开更多
随着当今电子行业的发展,对SoC芯片,尤其是数模混合芯片的要求越来越高。和传统的DEF/GDS数据交互方式相比,Mixed Signal Open Database(MSOA)RapidPDK可以帮助设计人员通过相同的PDK更好地完成数字工具Innovus和模拟工具Virtuoso之间...随着当今电子行业的发展,对SoC芯片,尤其是数模混合芯片的要求越来越高。和传统的DEF/GDS数据交互方式相比,Mixed Signal Open Database(MSOA)RapidPDK可以帮助设计人员通过相同的PDK更好地完成数字工具Innovus和模拟工具Virtuoso之间的数据传递。首先描述了5 nm MSOA RapidPDK生成方式,其次使用生成的PDK实现5 nm IP物理实现,同时验证MSOA flow对5 nm设计在版图完成和交付方面的速率提升。展开更多
5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries.In a typical 5 nm logic process,the Fin pitch is 22~27 nm,the contact-poly pitch(CPP)is 48?55 nm,and...5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries.In a typical 5 nm logic process,the Fin pitch is 22~27 nm,the contact-poly pitch(CPP)is 48?55 nm,and the minimum metal pitch(MPP)is around 30~36 nm.Due to the fact that these pitches are much smaller than the resolution capability of 193 nm immersion lithography,it is also the first generation which adopts EUV photolithography technology on a large-scale where the process flow can be simplified by single exposure method from more than 10 layers.Relentless scaling brings big challenges to process integration and pushes each process module to the physical and material limit.Therefore,the success of process development will largely depend on careful balance the pros and cons to achieve both performance and yield targets.In the paper,we discussed the advantages and disadvantages of different process approaches for key process loops for 5 nm logic process flow,including dummy poly cut versus metal gate cut approaches in the metal gate loops,self-aligned contact(SAC)versus brutally aligned contact(BAC)approaches,and also introduced the self-aligned double patterning approach in the lower metal processes.Based on the above evaluation,we will provide a recommendation for module's process development.展开更多
With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have eme...With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node.The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates.Due to the relatively more mature process and rich learning of the device physics,the FinFET is still extended to 5 nm technology node.In this paper,we proposed a 5 nm FINFET device,which is based on typical 5 nm logic design rules.To achieve the challenging device performance target,which is around 15%speed gain or 25%power reduction against the 7 nm device,we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability.Based on our preferred device architecture,we provide our brief process flow,key dimensions,and simulated device DC/AC performance,like Vt,Idsat,SS,DIBL and parasitic parameters.As a part of the final evaluation,RO simulation result has been checked,which demonstrates that the Performance Per Area(PPA)is close to industry reference 5 nm performance.展开更多
Subject Code:F01With the support by the National Natural Science Foundation of China,the research team led by Prof.Peng Lianmao(彭练矛)and Prof.Zhang Zhiyong(张志勇)at the Key Laboratory for the Physics and Chemistry ...Subject Code:F01With the support by the National Natural Science Foundation of China,the research team led by Prof.Peng Lianmao(彭练矛)and Prof.Zhang Zhiyong(张志勇)at the Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics,Peking University,Beijing,recently reported that carbon nanotube CMOS FETs were scaled down to the 5nm gate length and presented展开更多
文摘5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet(EUV)lithography on a large scale.We have done a simulation study for typical 5 nm logic design rule patterns.In a 5 nm logic photo process,the most appropriate layers for the EUV lithography are the cut layers,metal layers,and via layers.Generally speaking,critical structures in a lithography process are semi-dense patterns,also known as the“forbidden pitch”patterns,the array edge structures,tip-to-tip structures,tip-to-line structures(under 2D design rules),the minimum area structures,the bi-lines,tri-lines,…,etc.Compared to that from the 193 nm immersion process,the behaviors for the above structures are different.For example,in the 193 nm immersion process,the minimum area is about 2~3 times that of minimum pixel squared,while in EUV photolithographic process,the minimum achievable area is found to be significantly larger.In the simulation,we have kept aware of the stochastics impact due to drastically reduced number of photons absorbed compared to the DUV process,the criteria used for various structures of image contrast are tightened.For example,in 193 nm immersion lithography,we have usually set the minimum Exposure Latitude(EL)for the poly layer,the metal layer,and tip-to-tip pattern,respectively,at 18%,13%,and 10%.However,in EUV lithography,reasonable targets for the minima are,respectively,>18%,18%,and 13%.We have also studied the aberration and shadowing impact to the above design rule structures.We will present the results of our work and our explanations.
基金I thank the higher management team from Shanghai IC R&D Company for the support of this work.
文摘5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries.In a typical 5 nm logic process,the Fin pitch is 22~27 nm,the contact-poly pitch(CPP)is 48?55 nm,and the minimum metal pitch(MPP)is around 30~36 nm.Due to the fact that these pitches are much smaller than the resolution capability of 193 nm immersion lithography,it is also the first generation which adopts EUV photolithography technology on a large-scale where the process flow can be simplified by single exposure method from more than 10 layers.Relentless scaling brings big challenges to process integration and pushes each process module to the physical and material limit.Therefore,the success of process development will largely depend on careful balance the pros and cons to achieve both performance and yield targets.In the paper,we discussed the advantages and disadvantages of different process approaches for key process loops for 5 nm logic process flow,including dummy poly cut versus metal gate cut approaches in the metal gate loops,self-aligned contact(SAC)versus brutally aligned contact(BAC)approaches,and also introduced the self-aligned double patterning approach in the lower metal processes.Based on the above evaluation,we will provide a recommendation for module's process development.
基金The authors would like to thank the management team and all our team members in Shanghai ICRD center.
文摘With the continuous scaling in conventional CMOS technologies,the planar MOSFET device is limited by the severe short-channel-effect(SCE),Multi-gate FETs(MuG-FET)such as FinFETs and Nanowire,Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node.The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates.Due to the relatively more mature process and rich learning of the device physics,the FinFET is still extended to 5 nm technology node.In this paper,we proposed a 5 nm FINFET device,which is based on typical 5 nm logic design rules.To achieve the challenging device performance target,which is around 15%speed gain or 25%power reduction against the 7 nm device,we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability.Based on our preferred device architecture,we provide our brief process flow,key dimensions,and simulated device DC/AC performance,like Vt,Idsat,SS,DIBL and parasitic parameters.As a part of the final evaluation,RO simulation result has been checked,which demonstrates that the Performance Per Area(PPA)is close to industry reference 5 nm performance.
文摘Subject Code:F01With the support by the National Natural Science Foundation of China,the research team led by Prof.Peng Lianmao(彭练矛)and Prof.Zhang Zhiyong(张志勇)at the Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics,Peking University,Beijing,recently reported that carbon nanotube CMOS FETs were scaled down to the 5nm gate length and presented
