A novel parameter extraction technique suitable f or short channel length lightly-doped-drain (LDD) MOSFET's is proposed which seg ments the total gate bias range,and executes the linear regression in every subs ...A novel parameter extraction technique suitable f or short channel length lightly-doped-drain (LDD) MOSFET's is proposed which seg ments the total gate bias range,and executes the linear regression in every subs ections,yielding the gate bias dependent parameters,such as effective channel le ngth,parasitic resistance,and mobility,etc.This method avoids the gate bias rang e optimization,and retains the accuracy and simplicity of linear regression.The extracted gate bias dependent parameters are implemented in the compact I-V model which has been proposed for deep submicron LDD MOSFET's.The good agreemen ts between simulations and measurements of the devices on 0.18μm CMOS technolo gy indicate the effectivity of this technique.展开更多
A novel substrate current model is proposed for submicron and deep-submicron li ghtly-doped-drain (LDD) n-MOSFET,with the emphasis on accurate description of the characteristics length by taking the effects of channe...A novel substrate current model is proposed for submicron and deep-submicron li ghtly-doped-drain (LDD) n-MOSFET,with the emphasis on accurate description of the characteristics length by taking the effects of channel length and bias int o account.This is due to that the characteristics lenth significantly affects th e maximum lateral electric field and the length of velocity saturation region,bo th of which are very important in modeling the drain current and the substrate c urrent.The comparison between simulations and experiments shows a good predictio n of the model for submicron and deep-submicron LDD MOSFET.Moreover,the analyti cal model is suitable for descgn of devices as it is low in computation consumpt ion.展开更多
文摘A novel parameter extraction technique suitable f or short channel length lightly-doped-drain (LDD) MOSFET's is proposed which seg ments the total gate bias range,and executes the linear regression in every subs ections,yielding the gate bias dependent parameters,such as effective channel le ngth,parasitic resistance,and mobility,etc.This method avoids the gate bias rang e optimization,and retains the accuracy and simplicity of linear regression.The extracted gate bias dependent parameters are implemented in the compact I-V model which has been proposed for deep submicron LDD MOSFET's.The good agreemen ts between simulations and measurements of the devices on 0.18μm CMOS technolo gy indicate the effectivity of this technique.
文摘A novel substrate current model is proposed for submicron and deep-submicron li ghtly-doped-drain (LDD) n-MOSFET,with the emphasis on accurate description of the characteristics length by taking the effects of channel length and bias int o account.This is due to that the characteristics lenth significantly affects th e maximum lateral electric field and the length of velocity saturation region,bo th of which are very important in modeling the drain current and the substrate c urrent.The comparison between simulations and experiments shows a good predictio n of the model for submicron and deep-submicron LDD MOSFET.Moreover,the analyti cal model is suitable for descgn of devices as it is low in computation consumpt ion.
