A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET.Experimental results were used to validate this model.Th...A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET.Experimental results were used to validate this model.The extracted parameters from our model were tOX=20 nm,ND=1×1016cm 3,tSSi=13.2 nm,consistent with the experimental values.The results show that the simulation results agree with experimental data well.It is found that the plateau can be strongly affected by doping concentration,strained-Si layer thickness and mass fraction of Ge in the SiGe layer.The model has been implemented in the software for strained silicon MOSFET parameter extraction,and has great value in the design of the strained-Si/SiGe devices.展开更多
The effect of substrate doping on the threshold voltages of buried channel pMOSFET based on strained-SiGe technology was studied.By physically deriving the models of the threshold voltages,it is found that the layer w...The effect of substrate doping on the threshold voltages of buried channel pMOSFET based on strained-SiGe technology was studied.By physically deriving the models of the threshold voltages,it is found that the layer which inversely occurs first is substrate doping dependent,giving explanation for the variation of plateau observed in the C-V characteristics of this device,as the doping concentration increases.The threshold voltages obtained from the proposed model are-1.2805 V for buried channel and-2.9358 V for surface channel at a lightly doping case,and-3.41 V for surface channel at a heavily doping case,which agrees well with the experimental results.Also,the variations of the threshold voltages with several device parameters are discussed,which provides valuable reference to the designers of strained-SiGe devices.展开更多
The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method dir...The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.展开更多
This paper focuses on the study of thermal performances of MOS （metal-oxide-semiconductor） transistors for uncooled infrared bolometer applications. Such devices can be used in various applications both military and...This paper focuses on the study of thermal performances of MOS （metal-oxide-semiconductor） transistors for uncooled infrared bolometer applications. Such devices can be used in various applications both military and civil, such as defence and security, medical applications, industrial surveillance, etc. Series of measurements were conducted to obtain TCC （temperature coefficient of current） versus gate voltage and temperature curves. The TCC is a figure of merit for a device used as the sensitive element in a bolometer that represents its sensitivity to temperature and as such is a good indicator of the detector attainable performance. The measurements were confronted to Atlas simulations, and showed that in the subthreshold region the TCC ranges from 4%/K all the way to 9%/K which represents a great improvement compared to state of the art thermistor bolometers. Analytic expressions of the TCC are also derived from current equations of the MOSFET （MOS field effect transistor） drain current to help understanding the effect of drain to source voltage, mobility, temperature and threshold voltage sensibility to temperature, in all three operation modes of the transistor （subthreshold, ohmic and saturation）. It was also determined that gate length does not have an influence on the TCC until short channel effects are factored in.展开更多
基金Projects(51308040203,6139801)supported by National Ministries and Commissions,ChinaProjects(72105499,72104089)supported by the Fundamental Research Funds for the Central Universities,ChinaProject(2010JQ8008)supported by the Natural Science Basic Research Plan in Shaanxi Province of China
文摘A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET.Experimental results were used to validate this model.The extracted parameters from our model were tOX=20 nm,ND=1×1016cm 3,tSSi=13.2 nm,consistent with the experimental values.The results show that the simulation results agree with experimental data well.It is found that the plateau can be strongly affected by doping concentration,strained-Si layer thickness and mass fraction of Ge in the SiGe layer.The model has been implemented in the software for strained silicon MOSFET parameter extraction,and has great value in the design of the strained-Si/SiGe devices.
基金Projects(51308040203,6139801)supported by the National Ministries and CommissionsProjects(72105499,72104089)supported the Fundamental Research Funds for the Central Universities,ChinaProject(2010JQ8008)supported by the Natural Science Basic Research Plan in Shaanxi Province,China
文摘The effect of substrate doping on the threshold voltages of buried channel pMOSFET based on strained-SiGe technology was studied.By physically deriving the models of the threshold voltages,it is found that the layer which inversely occurs first is substrate doping dependent,giving explanation for the variation of plateau observed in the C-V characteristics of this device,as the doping concentration increases.The threshold voltages obtained from the proposed model are-1.2805 V for buried channel and-2.9358 V for surface channel at a lightly doping case,and-3.41 V for surface channel at a heavily doping case,which agrees well with the experimental results.Also,the variations of the threshold voltages with several device parameters are discussed,which provides valuable reference to the designers of strained-SiGe devices.
基金special funds of major state basic research projects (G20000365)
文摘The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.
文摘This paper focuses on the study of thermal performances of MOS （metal-oxide-semiconductor） transistors for uncooled infrared bolometer applications. Such devices can be used in various applications both military and civil, such as defence and security, medical applications, industrial surveillance, etc. Series of measurements were conducted to obtain TCC （temperature coefficient of current） versus gate voltage and temperature curves. The TCC is a figure of merit for a device used as the sensitive element in a bolometer that represents its sensitivity to temperature and as such is a good indicator of the detector attainable performance. The measurements were confronted to Atlas simulations, and showed that in the subthreshold region the TCC ranges from 4%/K all the way to 9%/K which represents a great improvement compared to state of the art thermistor bolometers. Analytic expressions of the TCC are also derived from current equations of the MOSFET （MOS field effect transistor） drain current to help understanding the effect of drain to source voltage, mobility, temperature and threshold voltage sensibility to temperature, in all three operation modes of the transistor （subthreshold, ohmic and saturation）. It was also determined that gate length does not have an influence on the TCC until short channel effects are factored in.
