In this paper, we investigate the factor properties and gap sequence of the Tri- bonacci sequence, the fixed point of the substitution σ（a, b, c） = （ab, ac, a）. Let Wp be the p-th occurrence of w and Gp（ω） be ...In this paper, we investigate the factor properties and gap sequence of the Tri- bonacci sequence, the fixed point of the substitution σ（a, b, c） = （ab, ac, a）. Let Wp be the p-th occurrence of w and Gp（ω） be the gap between Wp and Wp＋l. We introduce a notion of kernel for each factor w, and then give the decomposition of the factor w with respect to its kernel. Using the kernel and the decomposition, we prove the main result of this paper： for each factor w, the gap sequence {Gp（ω）}p≥1 is the Tribonacci sequence over the alphabet {G1 （ω）, G2（ω）, G4（ω）}, and the expressions of gaps are determined completely. As an application, for each factor w and p C ∈N, we determine the position of Wp. Finally we introduce a notion of spectrum for studying some typical combinatorial properties, such as power, overlap and separate of factors.展开更多
ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to ...ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms： Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer4evel （RTL） level as technology-independent reusable IP-cores. They are reconfigurable according to two compilemtime constants： set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.展开更多
The problem of improving the performance of linear programming（LP） decoding of low-density parity-check（LDPC） codes is considered in this paper.A multistep linear programming（MLP） algorithm was developed for dec...The problem of improving the performance of linear programming（LP） decoding of low-density parity-check（LDPC） codes is considered in this paper.A multistep linear programming（MLP） algorithm was developed for decoding LDPC codes that includes a slight increase in computational complexity.The MLP decoder adaptively adds new constraints which are compatible with a selected check node to refine the results when an error is reported by the original LP decoder.The MLP decoder result is shown to have the maximum-likelihood（ML） certificate property.Simulations with moderate block length LDPC codes suggest that the MLP decoder gives better performance than both the original LP decoder and the conventional sum-product（SP） decoder.展开更多
基金supported by grants from the National Science Foundation of China(114310071127122311371210)
文摘In this paper, we investigate the factor properties and gap sequence of the Tri- bonacci sequence, the fixed point of the substitution σ（a, b, c） = （ab, ac, a）. Let Wp be the p-th occurrence of w and Gp（ω） be the gap between Wp and Wp＋l. We introduce a notion of kernel for each factor w, and then give the decomposition of the factor w with respect to its kernel. Using the kernel and the decomposition, we prove the main result of this paper： for each factor w, the gap sequence {Gp（ω）}p≥1 is the Tribonacci sequence over the alphabet {G1 （ω）, G2（ω）, G4（ω）}, and the expressions of gaps are determined completely. As an application, for each factor w and p C ∈N, we determine the position of Wp. Finally we introduce a notion of spectrum for studying some typical combinatorial properties, such as power, overlap and separate of factors.
文摘ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms： Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer4evel （RTL） level as technology-independent reusable IP-cores. They are reconfigurable according to two compilemtime constants： set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.
基金Supported by the National Key Basic Research and Development (973) Program of China (No.2009CB320300)
文摘The problem of improving the performance of linear programming（LP） decoding of low-density parity-check（LDPC） codes is considered in this paper.A multistep linear programming（MLP） algorithm was developed for decoding LDPC codes that includes a slight increase in computational complexity.The MLP decoder adaptively adds new constraints which are compatible with a selected check node to refine the results when an error is reported by the original LP decoder.The MLP decoder result is shown to have the maximum-likelihood（ML） certificate property.Simulations with moderate block length LDPC codes suggest that the MLP decoder gives better performance than both the original LP decoder and the conventional sum-product（SP） decoder.
