This paper proposes an oxide filled extended trench gate super junction （SJ） MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, ne...This paper proposes an oxide filled extended trench gate super junction （SJ） MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication.展开更多
In this paper,a novel trench gate gallium nitride(GaN)insulated gate bipolar transistor(GaN IGBT),in which the collector is divided into multiple regions to control the hole injection efficiency,is designed and theore...In this paper,a novel trench gate gallium nitride(GaN)insulated gate bipolar transistor(GaN IGBT),in which the collector is divided into multiple regions to control the hole injection efficiency,is designed and theoretically studied.The incorporation of a P+/P-multi-region alternating structure in the collector region mitigates hole injection within the collector region.When the device is in forward conduction,the conductivity modulation effect results in a reduced storage of carriers in the drift region.As a result,the number of carriers requiring extraction during device turn-off is minimized,leading to a faster turn-off speed.The results illustrate that the GaN IGBT with controlled hole injection efficiency(CEH GaN IGBT)exhibits markedly enhanced performance compared to conventional GaN IGBT,showing a remarkable 42.2%reduction in turn-off time and a notable 28.5%decrease in turn-off loss.展开更多
In this paper,a novel superjunction 4H-silicon carbide(4H-SiC)trench-gate insulated-gate bipolar transistor(IGBT)featuring an integrated clamping PN diode between the P-shield and emitter(TSD-IGBT)is designed and theo...In this paper,a novel superjunction 4H-silicon carbide(4H-SiC)trench-gate insulated-gate bipolar transistor(IGBT)featuring an integrated clamping PN diode between the P-shield and emitter(TSD-IGBT)is designed and theoretically studied.The heavily doping superjunction layer contributes to a low specific on-resistance,excellent electric field distribution,and quasi-unipolar drift current.The anode of the clamping diode is in floating contact with the P-shield.In the on-state,the potential of the P-shield is raised to the turn-on voltage of the clamping diode,which prevents the hole extraction below the N-type carrier storage layer(NCSL).Additionally,during the turn-off transient,once the clamping diode is turned on,it also promotes an additional hole extraction path.Furthermore,the potential dropped at the semiconductor near the trench-gate oxide is effectively reduced in the off-state.展开更多
Based on the construction of the 8-inch fabricat ion line, advanced process technology of 8-inch wafer, as well as the fourth-generation high-voltage double-diffused metal-oxide semiconductor(DMOS+) insulated-gate bip...Based on the construction of the 8-inch fabricat ion line, advanced process technology of 8-inch wafer, as well as the fourth-generation high-voltage double-diffused metal-oxide semiconductor(DMOS+) insulated-gate bipolar transistor(IGBT) technology and the fifth-generation trench gate IGBT technology, have been developed, realizing a great-leap forward technological development for the manufacturing of high-voltage IGBT from 6-inch to 8-inch. The 1600 A/1.7 kV and 1500 A/3.3 kV IGBT modules have been successfully fabricated, qualified, and applied in rail transportation traction system.展开更多
A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations....A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.展开更多
We propose a novel high performance carrier stored trench bipolar transistor(CSTBT)with dual shielding structure(DSS-CSTBT).The proposed DSS-CSTBT features a double trench structure with different trench profiles in t...We propose a novel high performance carrier stored trench bipolar transistor(CSTBT)with dual shielding structure(DSS-CSTBT).The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface,in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it.Compared with the conventional CSTBT(con-CSTBT),the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage(BV),but also well reduces the gate-collector capacitance CGC,gate charge Q_(G),and turn-off loss E_(OFF)of the device.Furthermore,lower turn-on loss E_(ON)and gate drive loss E_(DR)are also obtained.Simulation results show that with the same CS layer doping concentration N_(CS)=1.5×10^(16)cm^(-3),the BV increases from 1312 V of the con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate(T_(og2))of 1μm.Moreover,compared with the con-CSTBT,the C_(GC)at V_(CE)of 25 V and miller plateau charge(Q_(GC))for the proposed DSS-CSTBT with T_(og2)of 1μm are reduced by 79.4%and 74.3%,respectively.With the VGEincreases from 0 V to 15 V,the total QGfor the proposed DSS-CSTBT with T_(og2)of 1μm is reduced by 49.5%.As a result,at the same on-state voltage drop(V_(CEON))of 1.55 V,the E_(ON)and E_(OFF)are reduced from 20.3 mJ/cm^(2)and 19.3 mJ/cm^(2)for the con-CSTBT to8.2 mJ/cm^(2)and 9.7 mJ/cm^(2)for the proposed DSS-CSTBT with T_(og2)of 1μm,respectively.The proposed DSS-CSTBT not only significantly improves the trade-off relationship between the V_(CEON)and E_(OFF)but also greatly reduces the E_(ON).展开更多
A low specific on-resistance （RS,on） silicon-on-insulator （SOI） trench MOSFET （nmtal-oxide-semiconductor-field- effect-transistor） with a reduced cell pitch is proposed. The lateral MOSFET features multiple tren...A low specific on-resistance （RS,on） silicon-on-insulator （SOI） trench MOSFET （nmtal-oxide-semiconductor-field- effect-transistor） with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches： two oxide trenches in the drift region and a trench gate extended to the buried oxide （BOX） （SOI MT MOSFET）. Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple=directional depletion, which improves the electric field distribution and enhances the reduced surface field （RESURF） effect in the SOI layer. Both of them result in a high breakdown voltage （BV）. Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced Rs,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor （LDMOS） to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩ cm2 to 36.6 mΩ. cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.展开更多
A low on-resistance （Ron,sp） integrable silicon-on-insulator （SOI） n-channel lateral double-diffused metal-oxide-semiconductor （LDMOS） is proposed and its mechanism is investigated by simulation. The LDMOS has t...A low on-resistance （Ron,sp） integrable silicon-on-insulator （SOI） n-channel lateral double-diffused metal-oxide-semiconductor （LDMOS） is proposed and its mechanism is investigated by simulation. The LDMOS has two features： the integration of a planar gate and an extended trench gate （double gates （DGs））; and a buried P-layer in the N-drift region, which forms a triple reduced surface field （RESURF） （TR） structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance （Ron,sp） and an improved breakdown voltage （BV） in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor （MOSFET） by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.展开更多
An integrable silicon-on-insulator （SOl） power lateral MOSFET with a trench gate and a recessed drain （TGRD MOSFET） is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide （...An integrable silicon-on-insulator （SOl） power lateral MOSFET with a trench gate and a recessed drain （TGRD MOSFET） is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide （BOX） and the recessed drain reduce the specific on-resistance （Ron, sp） by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage （BV） of 97 V and Ron, sp of 0.985 mf2-cm2 （l/os = 5 V） are obtained for a TGRD MOSFET with 6.5/xm half-cell pitch. Compared with the trench gate SOI MOSFET （TG MOSFET） and the conventional MOSFET, Ron＇ sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain （TGTD MOSFET）, BV of the TGRD MOSFET increases by 37% at the same Ron,sp.展开更多
An improved breakdown voltage （BV） SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenc...An improved breakdown voltage （BV） SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches （DTMOS）, an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide （BOX）. The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide （eox） than that of Si （esi）. Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF （reduced surface field） effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit （HVIC）, effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.展开更多
A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and...A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.展开更多
An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench（HK TG VDMOS） is proposed in this paper.The HK TG VDMOS features a hi...An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench（HK TG VDMOS） is proposed in this paper.The HK TG VDMOS features a high-k（HK） trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage（BV）.Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction（SJ） vertical double-diffused metal-oxide semiconductor（VDMOS）,the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS（TG VDMOS） and conventional superjunction trench gate VDMOS（SJ TG CDMOS）.展开更多
基金supported by the Doctor Scientific Research Start-up Foundation of Xi'an University of Technology of China
文摘This paper proposes an oxide filled extended trench gate super junction （SJ） MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication.
基金the General Program of Natural Science Foundation of Chongqing(CSTB2023NSCQ-MSX0475)the Doctoral Research Start-up Fund of Chongqing University of Posts and Telecommunications(A2023-70)。
文摘In this paper,a novel trench gate gallium nitride(GaN)insulated gate bipolar transistor(GaN IGBT),in which the collector is divided into multiple regions to control the hole injection efficiency,is designed and theoretically studied.The incorporation of a P+/P-multi-region alternating structure in the collector region mitigates hole injection within the collector region.When the device is in forward conduction,the conductivity modulation effect results in a reduced storage of carriers in the drift region.As a result,the number of carriers requiring extraction during device turn-off is minimized,leading to a faster turn-off speed.The results illustrate that the GaN IGBT with controlled hole injection efficiency(CEH GaN IGBT)exhibits markedly enhanced performance compared to conventional GaN IGBT,showing a remarkable 42.2%reduction in turn-off time and a notable 28.5%decrease in turn-off loss.
基金the General Program of National Natural Science Foundation of Chongqing(CSTB2023NSCQ-MSX0475)the Doctoral Research Start-up Fund of Chongqing University of Posts and Telecommunications(A2023-7)the Technology Innovation and Application Demonstration Key Project of Chongqing Municipality(cstc2019jszx-zdztzxX0005,cstc2020jscx-gksbX0011)。
文摘In this paper,a novel superjunction 4H-silicon carbide(4H-SiC)trench-gate insulated-gate bipolar transistor(IGBT)featuring an integrated clamping PN diode between the P-shield and emitter(TSD-IGBT)is designed and theoretically studied.The heavily doping superjunction layer contributes to a low specific on-resistance,excellent electric field distribution,and quasi-unipolar drift current.The anode of the clamping diode is in floating contact with the P-shield.In the on-state,the potential of the P-shield is raised to the turn-on voltage of the clamping diode,which prevents the hole extraction below the N-type carrier storage layer(NCSL).Additionally,during the turn-off transient,once the clamping diode is turned on,it also promotes an additional hole extraction path.Furthermore,the potential dropped at the semiconductor near the trench-gate oxide is effectively reduced in the off-state.
文摘Based on the construction of the 8-inch fabricat ion line, advanced process technology of 8-inch wafer, as well as the fourth-generation high-voltage double-diffused metal-oxide semiconductor(DMOS+) insulated-gate bipolar transistor(IGBT) technology and the fifth-generation trench gate IGBT technology, have been developed, realizing a great-leap forward technological development for the manufacturing of high-voltage IGBT from 6-inch to 8-inch. The 1600 A/1.7 kV and 1500 A/3.3 kV IGBT modules have been successfully fabricated, qualified, and applied in rail transportation traction system.
基金the National Natural Science Foundation of China (Grant Nos. 61774052 and 61904045)the National Research and Development Program for Major Research Instruments of China (Grant No. 62027814)the Natural Science Foundation of Jiangxi Province, China (Grant No. 20212BAB214047)。
文摘A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.
基金the National Key Research and Development Program of China(Grant No.2018YFB1201802)the Key Realm R&D Program of Guangdong Province,China(Grant No.2018B010142001)the Guangdong Basic and Applied Basic Research Foundation,China(Grant No.2020A1515010128).
文摘We propose a novel high performance carrier stored trench bipolar transistor(CSTBT)with dual shielding structure(DSS-CSTBT).The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface,in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it.Compared with the conventional CSTBT(con-CSTBT),the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage(BV),but also well reduces the gate-collector capacitance CGC,gate charge Q_(G),and turn-off loss E_(OFF)of the device.Furthermore,lower turn-on loss E_(ON)and gate drive loss E_(DR)are also obtained.Simulation results show that with the same CS layer doping concentration N_(CS)=1.5×10^(16)cm^(-3),the BV increases from 1312 V of the con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate(T_(og2))of 1μm.Moreover,compared with the con-CSTBT,the C_(GC)at V_(CE)of 25 V and miller plateau charge(Q_(GC))for the proposed DSS-CSTBT with T_(og2)of 1μm are reduced by 79.4%and 74.3%,respectively.With the VGEincreases from 0 V to 15 V,the total QGfor the proposed DSS-CSTBT with T_(og2)of 1μm is reduced by 49.5%.As a result,at the same on-state voltage drop(V_(CEON))of 1.55 V,the E_(ON)and E_(OFF)are reduced from 20.3 mJ/cm^(2)and 19.3 mJ/cm^(2)for the con-CSTBT to8.2 mJ/cm^(2)and 9.7 mJ/cm^(2)for the proposed DSS-CSTBT with T_(og2)of 1μm,respectively.The proposed DSS-CSTBT not only significantly improves the trade-off relationship between the V_(CEON)and E_(OFF)but also greatly reduces the E_(ON).
基金supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060)the Science Fund of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904)the Innovation Foundation of the State Key Laboratory of Electronic Thin Films and Integrated Devices (Grant No. CXJJ201004)
文摘A low specific on-resistance （RS,on） silicon-on-insulator （SOI） trench MOSFET （nmtal-oxide-semiconductor-field- effect-transistor） with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches： two oxide trenches in the drift region and a trench gate extended to the buried oxide （BOX） （SOI MT MOSFET）. Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple=directional depletion, which improves the electric field distribution and enhances the reduced surface field （RESURF） effect in the SOI layer. Both of them result in a high breakdown voltage （BV）. Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced Rs,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor （LDMOS） to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩ cm2 to 36.6 mΩ. cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 609 76060)the National Key Laboratory of Analogue Integrated Circuit (Grant No. 9140C090304110C0905)
文摘A low on-resistance （Ron,sp） integrable silicon-on-insulator （SOI） n-channel lateral double-diffused metal-oxide-semiconductor （LDMOS） is proposed and its mechanism is investigated by simulation. The LDMOS has two features： the integration of a planar gate and an extended trench gate （double gates （DGs））; and a buried P-layer in the N-drift region, which forms a triple reduced surface field （RESURF） （TR） structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance （Ron,sp） and an improved breakdown voltage （BV） in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor （MOSFET） by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.
基金supported by the National Natural Science Foundation of China(Nos.60976060,61176069)the National Key Laboratory of AnalogIntegrated Circuit(NLAIC),China(No.9140C090304110C0905)the State Key Laboratory of Electronic Thin Films and Integrated Devices,China(No.CXJJ201004)
文摘An integrable silicon-on-insulator （SOl） power lateral MOSFET with a trench gate and a recessed drain （TGRD MOSFET） is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide （BOX） and the recessed drain reduce the specific on-resistance （Ron, sp） by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage （BV） of 97 V and Ron, sp of 0.985 mf2-cm2 （l/os = 5 V） are obtained for a TGRD MOSFET with 6.5/xm half-cell pitch. Compared with the trench gate SOI MOSFET （TG MOSFET） and the conventional MOSFET, Ron＇ sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain （TGTD MOSFET）, BV of the TGRD MOSFET increases by 37% at the same Ron,sp.
基金Projects supported by the National Natural Science Foundation of China(No.61176069)the Special Financial Gnants from the China Postdoctoral Science Foundation and Chongqing(Nos.2012T50771,XM2012004)
文摘An improved breakdown voltage （BV） SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches （DTMOS）, an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide （BOX）. The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide （eox） than that of Si （esi）. Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF （reduced surface field） effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit （HVIC）, effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.
基金Project supported by the National Natural Science Foundation of China (Grant No. 61176069)the National Key Laboratory of Analog Integrated Circuit,China (Grant No. 9140C090304110C0905)the Innovation Foundation of the State Key Laboratory of Electronic Thin Films and Integrated Devices,China (Grant No. CXJJ201004)
文摘A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 61176069 )the Program for New Century Excellent Talents in University of Ministry of Education of China (Grant No. NCET-11-0062)
文摘An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench（HK TG VDMOS） is proposed in this paper.The HK TG VDMOS features a high-k（HK） trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage（BV）.Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction（SJ） vertical double-diffused metal-oxide semiconductor（VDMOS）,the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS（TG VDMOS） and conventional superjunction trench gate VDMOS（SJ TG CDMOS）.
