To facilitate the application of support vector machines (SVMs) in embedded systems,we propose and test a parallel and scalable digital architecture based on the sequential minimal optimization (SMO) algorithm for tra...To facilitate the application of support vector machines (SVMs) in embedded systems,we propose and test a parallel and scalable digital architecture based on the sequential minimal optimization (SMO) algorithm for training SVMs.By taking advantage of the mature and popular SMO algorithm,the numerical instability issues that may exist in traditional numerical algorithms are avoided.The error cache updating task,which dominates the computation time of the algorithm,is mapped into multiple processing units working in parallel.Experiment results show that using the proposed architecture,SVM training problems can be solved effectively with inexpensive fixed-point arithmetic and good scalability can be achieved.This architecture overcomes the drawbacks of the previously proposed SVM hardware that lacks the necessary flexibility for embedded applications,and thus is more suitable for embedded use,where scalability is an important concern.展开更多
Support vector machines （SVMs） are initially designed for binary classification. How to effectively extend them for multiclass classification is still an ongoing research topic. A multiclass classifier is constructe...Support vector machines （SVMs） are initially designed for binary classification. How to effectively extend them for multiclass classification is still an ongoing research topic. A multiclass classifier is constructed by combining SVM^light algorithm with directed acyclic graph SVM （DAGSVM） method, named DAGSVM^light A new method is proposed to select the working set which is identical to the working set selected by SVM^light approach. Experimental results indicate DAGSVM^light is competitive with DAGSMO. It is more suitable for practice use. It may be an especially useful tool for large-scale multiclass classification problems and lead to more widespread use of SVMs in the engineering community due to its good performance.展开更多
基金Project (No.60720106003) supported by the National Natural Science Foundation of China
文摘To facilitate the application of support vector machines (SVMs) in embedded systems,we propose and test a parallel and scalable digital architecture based on the sequential minimal optimization (SMO) algorithm for training SVMs.By taking advantage of the mature and popular SMO algorithm,the numerical instability issues that may exist in traditional numerical algorithms are avoided.The error cache updating task,which dominates the computation time of the algorithm,is mapped into multiple processing units working in parallel.Experiment results show that using the proposed architecture,SVM training problems can be solved effectively with inexpensive fixed-point arithmetic and good scalability can be achieved.This architecture overcomes the drawbacks of the previously proposed SVM hardware that lacks the necessary flexibility for embedded applications,and thus is more suitable for embedded use,where scalability is an important concern.
文摘Support vector machines （SVMs） are initially designed for binary classification. How to effectively extend them for multiclass classification is still an ongoing research topic. A multiclass classifier is constructed by combining SVM^light algorithm with directed acyclic graph SVM （DAGSVM） method, named DAGSVM^light A new method is proposed to select the working set which is identical to the working set selected by SVM^light approach. Experimental results indicate DAGSVM^light is competitive with DAGSMO. It is more suitable for practice use. It may be an especially useful tool for large-scale multiclass classification problems and lead to more widespread use of SVMs in the engineering community due to its good performance.
