Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed an...Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.展开更多
This paper presents a fully on-chip NMOS low-dropout regulator（LDO） for portable applications with quasi floating gate pass element and fast transient response.The quasi floating gate structure makes the gate of the...This paper presents a fully on-chip NMOS low-dropout regulator（LDO） for portable applications with quasi floating gate pass element and fast transient response.The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump,which allows the charge pump to be a small economical circuit with small silicon area.In addition,a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient.The proposed LDO has been implemented in a 0.35 μm BCD process.From experimental results,the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and Iq of 395 μA.Under full-range load current step,the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV,respectively.展开更多
文摘Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.
文摘This paper presents a fully on-chip NMOS low-dropout regulator（LDO） for portable applications with quasi floating gate pass element and fast transient response.The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump,which allows the charge pump to be a small economical circuit with small silicon area.In addition,a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient.The proposed LDO has been implemented in a 0.35 μm BCD process.From experimental results,the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and Iq of 395 μA.Under full-range load current step,the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV,respectively.
