Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability.In battery-restricted applications such as handheld electronics systems,low...Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability.In battery-restricted applications such as handheld electronics systems,low-power FPGAs are in great demand.Leakage power almost equals dynamic power in modern integrated circuit technologies,so the reduction of leakage power leads to significant energy savings.We propose a power-efficient architecture for static random access memory(SRAM) based FPGAs,in which two modes (active mode and sleep mode) are defined for each module.In sleep mode,ultralow leakage power is consumed by the module.The module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input vectors.After producing the correct outputs,the module returns to sleep mode.The proposed circuit design reduces the leakage power consumption in both active and sleep modes.The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina(MCNC) benchmark circuits on FPGA-SPICE software.Simulation results show an approximately 95%reduction in leakage power consumption in sleep mode.Moreover,the total power consumption (leakage+dynamic power consumption) is reduced by more than 15%compared with that of the best previous design.The average area overhead (4.26%) is less than those of other powergating designs.展开更多
A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to allevi...A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.展开更多
设计了一个能对10 Hz^60 k Hz的声波信号进行精确程控滤波器系统,该系统采用STM32F103单片机作为控制核心,使用精密运放NE5532构成电压跟随缓冲部分,提高了系统滤波的精确性。程控滤波器采用CMOS双二阶通用开关电容有源滤波器MAX262构成...设计了一个能对10 Hz^60 k Hz的声波信号进行精确程控滤波器系统,该系统采用STM32F103单片机作为控制核心,使用精密运放NE5532构成电压跟随缓冲部分,提高了系统滤波的精确性。程控滤波器采用CMOS双二阶通用开关电容有源滤波器MAX262构成,可通过微处理器STM32F103精确控制滤波器的传递函数,在不需外部元件的情况下就可以构成各种带通、低通以及高通滤波器;系统性能指标精度比较高,工作可靠,人机交互以及用户界面非常友好。展开更多
Implementing self-sustainable wireless communication systems is urgent and challenging for 5G and 6G technologies.In this paper,we elaborate on a system solution using the programmable metasurface(PMS)for simultaneous...Implementing self-sustainable wireless communication systems is urgent and challenging for 5G and 6G technologies.In this paper,we elaborate on a system solution using the programmable metasurface(PMS)for simultaneous wireless information and power transfers(SWIPT),offering an optimized wireless energy management network.Both transmitting and receiving sides of the proposed solution are presented in detail.On the transmitting side,employing the wireless power transfer(WPT)technique,we present versatile power conveying strategies for near-field or far-field targets,single or multiple targets,and equal or unequal power targets.On the receiving side,utilizing the wireless energy harvesting(WEH)technique,we report our work on multi-functional rectifying metasurfaces that collect the wirelessly transmitted energy and the ambient energy.More importantly,a numerical model based on the plane-wave angular spectrum method is investigated to accurately calculate the radiation fields of PMS in the Fresnel and Fraunhofer regions.With this model,the efficiencies of WPT between the transmitter and the receiver are analyzed.Finally,future research directions are discussed,and integrated PMS for wireless information and wireless power is outlined.展开更多
The feasibility of a new full bridge high intensity focused ultrasound(HIFU) amplifier system with harmonic cancellation is evaluated in this study. Harmonic cancellation technique is applied to these power amplifiers...The feasibility of a new full bridge high intensity focused ultrasound(HIFU) amplifier system with harmonic cancellation is evaluated in this study. Harmonic cancellation technique is applied to these power amplifiers, which can eliminate the 3rd harmonic and all even harmonics. Since this technique requires two channels of phase signal to control one channel of power amplifier, the signal generator is required to double its output. The transducer array proposed in this study has 100 elements. So we choose an FPGA chip to generate 200 driving signals, and each channel has a phase resolution of 2ns, less than 1°. The phase signal from the FPGA meets the requirement of driving the power amplifiers. The output waveform of one channel of power amplifier(voltage across the transducer) is evaluated, and shows fewer harmonic components.展开更多
A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POT...A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.展开更多
This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonline...This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonlinearity of the concurrent dual-band power amplifier （PA）. This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables （LUTs） sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio （ACPR） is less than -59 dBc and normalized mean square error （NMSE） is around - 62dB for lower sideband （LSB） and - 63dB for upper sideband （USB）.展开更多
文摘Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and reconfigurability.In battery-restricted applications such as handheld electronics systems,low-power FPGAs are in great demand.Leakage power almost equals dynamic power in modern integrated circuit technologies,so the reduction of leakage power leads to significant energy savings.We propose a power-efficient architecture for static random access memory(SRAM) based FPGAs,in which two modes (active mode and sleep mode) are defined for each module.In sleep mode,ultralow leakage power is consumed by the module.The module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input vectors.After producing the correct outputs,the module returns to sleep mode.The proposed circuit design reduces the leakage power consumption in both active and sleep modes.The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina(MCNC) benchmark circuits on FPGA-SPICE software.Simulation results show an approximately 95%reduction in leakage power consumption in sleep mode.Moreover,the total power consumption (leakage+dynamic power consumption) is reduced by more than 15%compared with that of the best previous design.The average area overhead (4.26%) is less than those of other powergating designs.
文摘A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.
文摘设计了一个能对10 Hz^60 k Hz的声波信号进行精确程控滤波器系统,该系统采用STM32F103单片机作为控制核心,使用精密运放NE5532构成电压跟随缓冲部分,提高了系统滤波的精确性。程控滤波器采用CMOS双二阶通用开关电容有源滤波器MAX262构成,可通过微处理器STM32F103精确控制滤波器的传递函数,在不需外部元件的情况下就可以构成各种带通、低通以及高通滤波器;系统性能指标精度比较高,工作可靠,人机交互以及用户界面非常友好。
基金the National Key Research and Development Program of China under Grant Nos.2017YFA0700201,2017YFA0700202,2017YFA0700203,and 2021YFA1401001the 111 Project under Grant No.111⁃2⁃05,National Natural Science Foundation of China under Grant No.62001342+1 种基金Key Research and Development Program of Shaanxi under Grant No.2021TD⁃07Outstanding Youth Science Foundation of Shaanxi Province under Grant No.2019JC⁃15.
文摘Implementing self-sustainable wireless communication systems is urgent and challenging for 5G and 6G technologies.In this paper,we elaborate on a system solution using the programmable metasurface(PMS)for simultaneous wireless information and power transfers(SWIPT),offering an optimized wireless energy management network.Both transmitting and receiving sides of the proposed solution are presented in detail.On the transmitting side,employing the wireless power transfer(WPT)technique,we present versatile power conveying strategies for near-field or far-field targets,single or multiple targets,and equal or unequal power targets.On the receiving side,utilizing the wireless energy harvesting(WEH)technique,we report our work on multi-functional rectifying metasurfaces that collect the wirelessly transmitted energy and the ambient energy.More importantly,a numerical model based on the plane-wave angular spectrum method is investigated to accurately calculate the radiation fields of PMS in the Fresnel and Fraunhofer regions.With this model,the efficiencies of WPT between the transmitter and the receiver are analyzed.Finally,future research directions are discussed,and integrated PMS for wireless information and wireless power is outlined.
基金the National Natural Science Foundation of China(No.30800246)the Shanghai Key Technologies R&D Program of China(No.09441900500)the Research Program of Shanghai Education Commission(No.14CXY05)
文摘The feasibility of a new full bridge high intensity focused ultrasound(HIFU) amplifier system with harmonic cancellation is evaluated in this study. Harmonic cancellation technique is applied to these power amplifiers, which can eliminate the 3rd harmonic and all even harmonics. Since this technique requires two channels of phase signal to control one channel of power amplifier, the signal generator is required to double its output. The transducer array proposed in this study has 100 elements. So we choose an FPGA chip to generate 200 driving signals, and each channel has a phase resolution of 2ns, less than 1°. The phase signal from the FPGA meets the requirement of driving the power amplifiers. The output waveform of one channel of power amplifier(voltage across the transducer) is evaluated, and shows fewer harmonic components.
基金supported by the National Natural Science Foundation of China(Nos.61234002,61006028)the National High-Tech Program of China(Nos.2012AA012302,2013AA014103)the PhDProgram Foundation of Ministry of Education of China(No.20120203110017)
文摘A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.
基金supported by the National Natural Science Foundation of China(61201025)the National Natural Science Foundation of China for the Major Equipment Development(61327806)
文摘This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonlinearity of the concurrent dual-band power amplifier （PA）. This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables （LUTs） sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio （ACPR） is less than -59 dBc and normalized mean square error （NMSE） is around - 62dB for lower sideband （LSB） and - 63dB for upper sideband （USB）.
