The feature of Ternary Content Addressable Memories(TCAMs) makes them particularly attractive for IP address lookup and packet classification applications in a router system. However,the limitations of TCAMs impede th...The feature of Ternary Content Addressable Memories(TCAMs) makes them particularly attractive for IP address lookup and packet classification applications in a router system. However,the limitations of TCAMs impede their utilization. In this paper,the solutions for decreasing the power consumption and avoiding entry expansion in range matching are addressed. Experimental results demonstrate that the proposed techniques can make some big improvements on the performance of TCAMs in IP address lookup and packet classification.展开更多
Mainstream processors implement the instruction scheduler using a monolithic CAM-based issue queue （IQ）, which consumes increasingly high energy as its size scales. In particular, its instruction wakeup logic accoun...Mainstream processors implement the instruction scheduler using a monolithic CAM-based issue queue （IQ）, which consumes increasingly high energy as its size scales. In particular, its instruction wakeup logic accounts for a major portion of the consumed energy. Our study shows that instructions with 2 non-ready operands （called 2OP instructions） are in small percentage, but tend to spend long latencies in the IQ. They can be effectively shelved in a small RAM-based waiting instruction buffer （WIB） and steered into the IQ at appropriate time. With this two-level shelving ability, half of the CAM tag comparators are eliminated in the IQ, which significantly reduces the energy of wakeup operation. In addition, we propose an adaptive banking scheme to downsize the IQ and reduce the bit-width of tag comparators. Experiments indicate that for an 8-wide issue superscalar or SMT proeessor,the energy consumption of the instruction scheduler can be reduced by 67%. Furthermore, the new design has potentially faster scheduler clock speed while maintaining close IPC to the monolithic scheduler design. Compared with the previous work on eliminating tags through prediction, our design is superior in terms of both energy reduction and SMT support.展开更多
近年来闪存芯片(NANDFLASH)的生产技术获得了长足进步,单位芯片的存储容量及数据吞吐率不断提高.闪存芯片已经在移动终端领域成为主流的存储部件,例如在手机、数码相机、单片机等方面已经有了很广泛的应用.随着闪存成本的降低,其应用范...近年来闪存芯片(NANDFLASH)的生产技术获得了长足进步,单位芯片的存储容量及数据吞吐率不断提高.闪存芯片已经在移动终端领域成为主流的存储部件,例如在手机、数码相机、单片机等方面已经有了很广泛的应用.随着闪存成本的降低,其应用范围也逐渐扩展至大规模的数据存储系统中.针对在存储系统中闪存能耗预估准确性不高的问题,提出了一种基于能耗梯度的固态硬盘能耗建模方法,有效提升了固态硬盘(solid state disk, SSD)的能耗预测精度.首先根据SSD内部闪存芯片的层次结构及工作原理对SSD在读写过程中的能耗产生原因进行了分析和建模;其次将SSD内部的交错性及并行性作为建立能耗梯度列表的依据,使用测算结合的方法获得固态硬盘的能耗梯度列表,再根据能耗梯度去预测SSD的实时能耗.该建模方法所用的采集方法不会对系统带来额外的性能开销,适用于在线以及离线的SSD能耗预估.实验证明:与传统的线性能耗模型相比,该建模方法在读写操作的能耗预测精度上都有显著的提高.展开更多
基金the National Natural Science Foundation of China (No.60532030).
文摘The feature of Ternary Content Addressable Memories(TCAMs) makes them particularly attractive for IP address lookup and packet classification applications in a router system. However,the limitations of TCAMs impede their utilization. In this paper,the solutions for decreasing the power consumption and avoiding entry expansion in range matching are addressed. Experimental results demonstrate that the proposed techniques can make some big improvements on the performance of TCAMs in IP address lookup and packet classification.
文摘Mainstream processors implement the instruction scheduler using a monolithic CAM-based issue queue （IQ）, which consumes increasingly high energy as its size scales. In particular, its instruction wakeup logic accounts for a major portion of the consumed energy. Our study shows that instructions with 2 non-ready operands （called 2OP instructions） are in small percentage, but tend to spend long latencies in the IQ. They can be effectively shelved in a small RAM-based waiting instruction buffer （WIB） and steered into the IQ at appropriate time. With this two-level shelving ability, half of the CAM tag comparators are eliminated in the IQ, which significantly reduces the energy of wakeup operation. In addition, we propose an adaptive banking scheme to downsize the IQ and reduce the bit-width of tag comparators. Experiments indicate that for an 8-wide issue superscalar or SMT proeessor,the energy consumption of the instruction scheduler can be reduced by 67%. Furthermore, the new design has potentially faster scheduler clock speed while maintaining close IPC to the monolithic scheduler design. Compared with the previous work on eliminating tags through prediction, our design is superior in terms of both energy reduction and SMT support.
文摘近年来闪存芯片(NANDFLASH)的生产技术获得了长足进步,单位芯片的存储容量及数据吞吐率不断提高.闪存芯片已经在移动终端领域成为主流的存储部件,例如在手机、数码相机、单片机等方面已经有了很广泛的应用.随着闪存成本的降低,其应用范围也逐渐扩展至大规模的数据存储系统中.针对在存储系统中闪存能耗预估准确性不高的问题,提出了一种基于能耗梯度的固态硬盘能耗建模方法,有效提升了固态硬盘(solid state disk, SSD)的能耗预测精度.首先根据SSD内部闪存芯片的层次结构及工作原理对SSD在读写过程中的能耗产生原因进行了分析和建模;其次将SSD内部的交错性及并行性作为建立能耗梯度列表的依据,使用测算结合的方法获得固态硬盘的能耗梯度列表,再根据能耗梯度去预测SSD的实时能耗.该建模方法所用的采集方法不会对系统带来额外的性能开销,适用于在线以及离线的SSD能耗预估.实验证明:与传统的线性能耗模型相比,该建模方法在读写操作的能耗预测精度上都有显著的提高.
