This paper presents a comprehensive review of near-threshold wide-voltage designs on memory,resilient logic designs,low voltage Radio Frequency(RF)circuits,and timing analysis.With the prosperous development of wearab...This paper presents a comprehensive review of near-threshold wide-voltage designs on memory,resilient logic designs,low voltage Radio Frequency(RF)circuits,and timing analysis.With the prosperous development of wearable applications,low power consumption has become one of the primary challenges for IC designs.To improve the power efficiency,the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage(NTV).For the performance variation and degradation,a self-adaptive margin assignment technique is proposed in the low voltage.The proposed technique tracks the circuit states in real time and dynamically allocates voltage margins,reducing the minimum supply voltage and achieving higher energy efficiency.The self-adaptive margin assignment technique can be used in Static Random Access Memory(SRAM),digital circuits,and analog/RF circuits.Based on the self-adaptive margin assignment technique,the minimum voltage in the 40 nm CMOS process is reduced to 0.6 V or even lower,and the energy efficiency is increased by 3–4 times.展开更多
针对普通计算机自身时间频率稳定性较差、准确度较低的问题,提出一种利用外部硬件授时板卡同步计算机时间的设计方案。首先,将国际通用的美国靶场仪器组B型时间码(IRIG-B)或全球定位系统(GPS)信号接收机输出的时间信息作为参考时钟源来...针对普通计算机自身时间频率稳定性较差、准确度较低的问题,提出一种利用外部硬件授时板卡同步计算机时间的设计方案。首先,将国际通用的美国靶场仪器组B型时间码(IRIG-B)或全球定位系统(GPS)信号接收机输出的时间信息作为参考时钟源来同步授时板卡的本地时钟;其次,利用参考时钟源准时秒脉冲和板卡上晶振频率在时间误差上互补的特点,对多个连续秒脉冲间的晶振计数脉冲计数值进行动态平均,周期性求取晶振的实际频率;最后,利用分频模块结合晶振实际频率产生1 k Hz的外设部件互连(PCI)总线中断信号来将计算机时间同步到毫秒级。实际测试结果表明,当外部参考时钟源有效时,授时板卡本地时钟授时误差约为250 ns,利用晶振实际频率产生的PCI中断信号频率误差比直接利用晶振标称频率产生的PCI中断信号频率误差小40 Hz以上;当外部参考时钟源失效时,利用晶振实际频率产生的本地时钟自守时误差比利用晶振标称频率产生的本地时钟自守时误差小约20μs/min。利用晶振实际频率的设计方案相比直接利用晶振标称频率的设计方案能够有效减小计算机时间同步误差。展开更多
In orthogonal frequency division multiplexing （OFDM） systems, time and frequency synchronization are two critical elements for guaranteeing the orthogonality of OFDM subcarriers. Conventionally, with the employment ...In orthogonal frequency division multiplexing （OFDM） systems, time and frequency synchronization are two critical elements for guaranteeing the orthogonality of OFDM subcarriers. Conventionally, with the employment of pseudo-noise （PN） sequences in preamble design, the preamble information is not fully utilized in both symbol timing offset acquisition and carrier frequency offset estimation. In this article, a new synchronization algorithm is proposed for jointly optimizing the time and frequency synchronization. This algorithm uses polynomial sequences as synchronization preamble instead of PN sequences. Theoretical analysis and simulation results indicate that the proposed algorithm is much more accurate and reliable than other existing methods.展开更多
文摘This paper presents a comprehensive review of near-threshold wide-voltage designs on memory,resilient logic designs,low voltage Radio Frequency(RF)circuits,and timing analysis.With the prosperous development of wearable applications,low power consumption has become one of the primary challenges for IC designs.To improve the power efficiency,the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage(NTV).For the performance variation and degradation,a self-adaptive margin assignment technique is proposed in the low voltage.The proposed technique tracks the circuit states in real time and dynamically allocates voltage margins,reducing the minimum supply voltage and achieving higher energy efficiency.The self-adaptive margin assignment technique can be used in Static Random Access Memory(SRAM),digital circuits,and analog/RF circuits.Based on the self-adaptive margin assignment technique,the minimum voltage in the 40 nm CMOS process is reduced to 0.6 V or even lower,and the energy efficiency is increased by 3–4 times.
文摘针对普通计算机自身时间频率稳定性较差、准确度较低的问题,提出一种利用外部硬件授时板卡同步计算机时间的设计方案。首先,将国际通用的美国靶场仪器组B型时间码(IRIG-B)或全球定位系统(GPS)信号接收机输出的时间信息作为参考时钟源来同步授时板卡的本地时钟;其次,利用参考时钟源准时秒脉冲和板卡上晶振频率在时间误差上互补的特点,对多个连续秒脉冲间的晶振计数脉冲计数值进行动态平均,周期性求取晶振的实际频率;最后,利用分频模块结合晶振实际频率产生1 k Hz的外设部件互连(PCI)总线中断信号来将计算机时间同步到毫秒级。实际测试结果表明,当外部参考时钟源有效时,授时板卡本地时钟授时误差约为250 ns,利用晶振实际频率产生的PCI中断信号频率误差比直接利用晶振标称频率产生的PCI中断信号频率误差小40 Hz以上;当外部参考时钟源失效时,利用晶振实际频率产生的本地时钟自守时误差比利用晶振标称频率产生的本地时钟自守时误差小约20μs/min。利用晶振实际频率的设计方案相比直接利用晶振标称频率的设计方案能够有效减小计算机时间同步误差。
基金supported by Korean Electronics and Telecommunications Research Institute,the Hi-Tech Research and Development Program of China(2006AA01Z283)the Natural Science Foundation of China(60772113)
文摘In orthogonal frequency division multiplexing （OFDM） systems, time and frequency synchronization are two critical elements for guaranteeing the orthogonality of OFDM subcarriers. Conventionally, with the employment of pseudo-noise （PN） sequences in preamble design, the preamble information is not fully utilized in both symbol timing offset acquisition and carrier frequency offset estimation. In this article, a new synchronization algorithm is proposed for jointly optimizing the time and frequency synchronization. This algorithm uses polynomial sequences as synchronization preamble instead of PN sequences. Theoretical analysis and simulation results indicate that the proposed algorithm is much more accurate and reliable than other existing methods.
