With the increased design complexities brought in by applying different Reticle Enhancement Technologies (RETs) in nanometer-scale IC manufacturing process, post-RET sign-off verification is quickly becoming necessary...With the increased design complexities brought in by applying different Reticle Enhancement Technologies (RETs) in nanometer-scale IC manufacturing process, post-RET sign-off verification is quickly becoming necessary. By introducing innovative algorithms for lithographic modeling, silicon imaging and yield problem locating, this paper describes a new methodology of IC manufacturability verification based on Dense Silicon Imaging (DSI). Necessity of imaging based verification is analyzed. Existing post-RET verification methods are reviewed and compared to the new methodology. Due to the greatly improved computational efficiency produced by algorithms such as the ~16*log2N/log2M times faster Specialized FFT, DSI based manufacturability checks on full IC scale, which were impractical for applications before, are now realized. Real verification example has been demonstrated and studied as well.展开更多
In the sub-wavelength regime,design for manufacturability（DFM） becomes increasingly important for field programmable gate arrays（FPGAs）.In this paper,an automated tile generation flow targeting micro-regular fabri...In the sub-wavelength regime,design for manufacturability（DFM） becomes increasingly important for field programmable gate arrays（FPGAs）.In this paper,an automated tile generation flow targeting micro-regular fabric is reported.Using a publicly accessible,well-documented academic FPGA as a case study,we found that compared to the tile generators previously reported,our generated micro-regular tile incurs less than 10%area overhead,which could be potentially recovered by process window optimization,thanks to its superior printability. In addition,we demonstrate that on 45 nm technology,the generated FPGA tile reduces lithography induced process variation by 33%,and reduce probability of failure by 21.2%.If a further overhead of 10%area can be recovered by enhanced resolution,we can achieve the variation reduction of 93.8%and reduce the probability of failure by 16.2%.展开更多
This paper presents a method of designing a 65 nm DFM standard cell library.By reducing the amount of the library largely,the process of optical proximity correction（OPC） becomes more efficient and the need for larg...This paper presents a method of designing a 65 nm DFM standard cell library.By reducing the amount of the library largely,the process of optical proximity correction（OPC） becomes more efficient and the need for large storage is reduced.This library is more manufacture-friendly as each cell has been optimized according to the DFM rule and optical simulation.The area penalty is minor compared with traditional library,and the timing,as well as power has a good performance.Furthermore,this library has passed the test from the Technology Design Department of Foundry.The result shows this DFM standard cell library has advantages that improve the yield.展开更多
基金the National Natural Science Foundation of China(Grant Nos.60176015 , 90207002) the Hi—Tech R&D(863)Program of China(Grant Nos.2002AA1Z1460 , 2003AA1Z1370).
文摘With the increased design complexities brought in by applying different Reticle Enhancement Technologies (RETs) in nanometer-scale IC manufacturing process, post-RET sign-off verification is quickly becoming necessary. By introducing innovative algorithms for lithographic modeling, silicon imaging and yield problem locating, this paper describes a new methodology of IC manufacturability verification based on Dense Silicon Imaging (DSI). Necessity of imaging based verification is analyzed. Existing post-RET verification methods are reviewed and compared to the new methodology. Due to the greatly improved computational efficiency produced by algorithms such as the ~16*log2N/log2M times faster Specialized FFT, DSI based manufacturability checks on full IC scale, which were impractical for applications before, are now realized. Real verification example has been demonstrated and studied as well.
文摘In the sub-wavelength regime,design for manufacturability（DFM） becomes increasingly important for field programmable gate arrays（FPGAs）.In this paper,an automated tile generation flow targeting micro-regular fabric is reported.Using a publicly accessible,well-documented academic FPGA as a case study,we found that compared to the tile generators previously reported,our generated micro-regular tile incurs less than 10%area overhead,which could be potentially recovered by process window optimization,thanks to its superior printability. In addition,we demonstrate that on 45 nm technology,the generated FPGA tile reduces lithography induced process variation by 33%,and reduce probability of failure by 21.2%.If a further overhead of 10%area can be recovered by enhanced resolution,we can achieve the variation reduction of 93.8%and reduce the probability of failure by 16.2%.
基金supported by the National Major Specialized Program of China(Nos.2008ZX01035-001-07,2009ZX02023-4-2)
文摘This paper presents a method of designing a 65 nm DFM standard cell library.By reducing the amount of the library largely,the process of optical proximity correction（OPC） becomes more efficient and the need for large storage is reduced.This library is more manufacture-friendly as each cell has been optimized according to the DFM rule and optical simulation.The area penalty is minor compared with traditional library,and the timing,as well as power has a good performance.Furthermore,this library has passed the test from the Technology Design Department of Foundry.The result shows this DFM standard cell library has advantages that improve the yield.
