期刊文献+

Design for manufacturability of a VDSM standard cell library

Design for manufacturability of a VDSM standard cell library
原文传递
导出
摘要 This paper presents a method of designing a 65 nm DFM standard cell library.By reducing the amount of the library largely,the process of optical proximity correction(OPC) becomes more efficient and the need for large storage is reduced.This library is more manufacture-friendly as each cell has been optimized according to the DFM rule and optical simulation.The area penalty is minor compared with traditional library,and the timing,as well as power has a good performance.Furthermore,this library has passed the test from the Technology Design Department of Foundry.The result shows this DFM standard cell library has advantages that improve the yield. This paper presents a method of designing a 65 nm DFM standard cell library.By reducing the amount of the library largely,the process of optical proximity correction(OPC) becomes more efficient and the need for large storage is reduced.This library is more manufacture-friendly as each cell has been optimized according to the DFM rule and optical simulation.The area penalty is minor compared with traditional library,and the timing,as well as power has a good performance.Furthermore,this library has passed the test from the Technology Design Department of Foundry.The result shows this DFM standard cell library has advantages that improve the yield.
作者 Zhou Chong Chen Lan Zeng Jianping Yin Minghui Zhao Jie 周宠;陈岚;曾健平;尹明会;赵劼(College of Physics and Microelectronics Science,Hunan University,Changsha 410082,China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China)
出处 《Journal of Semiconductors》 EI CAS CSCD 2012年第2期143-148,共6页 半导体学报(英文版)
基金 supported by the National Major Specialized Program of China(Nos.2008ZX01035-001-07,2009ZX02023-4-2)
关键词 design for manufacturability reduced standard cell library layout optimization optical simulation YIELD design for manufacturability reduced standard cell library layout optimization optical simulation yield
  • 相关文献

参考文献10

  • 1Heineken H T, Khare J, Dareeu M. Maunfacturability analysis of standard cell libraries. Proc Custom Int Circ Conf, 1998:321. 被引量:1
  • 2Aitken R. DFM metrics for standard cells. IEEE Proceedings of the 7th International Symposium on Quality Electronic Design, 2006. 被引量:1
  • 3Duc N M, Sakurai T. Compact yet high-performance (CyHP) library for short time-to-market with new technologies. IEEE Asia and South Pacific Design Automation Conference, 2000:476. 被引量:1
  • 4Ricci A, de Munari I, Ciampolini P. Performance-effective com- paction of standard-cell libraries for digital design. IEEE 12th Euromicro Conference on Digital System Design/Architectures, Methods and Tools, 2009:315. 被引量:1
  • 5Jiao H L, Chen L. Cellwise OPC based on reduced standard cell library. IEEE 9th Intemational Symposium on Quality Electronic Design, 2008:810. 被引量:1
  • 6Sundareswaran S, Maziasz R, Rozenfeld V, et al. A sensitivity- aware methodology to improve cell layouts for DFM guidelines. IEEE 12th Int'l Symposium on Quality Electronic Design, 2011 : 431. 被引量:1
  • 7Jang D, Ha N, Park J H, et al. DFM optimization of standard cells considering random and systematic defect. IEEE Interna- tional SoC Design Conference, 2008:70. 被引量:1
  • 8Gupta P, Heng F L, Lavin M. Merits of cellwise model-based OPC. Proc SPIE, 2004, 5379:182. 被引量:1
  • 9Calibre Litho-Friendly Design User's Manual. Mentor Graphics Corporation, 2007. 被引量:1
  • 10Torres J A, Pikus F. Unified process-aware system for circuit layout verification. Proc SPIE Int Soc Opt Eng, 2007, 6521:652108. 被引量:1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部