The main electrical properties of advanced Silicon On Insulator MOSFETs are addressed. The subthreshold and high field operations are analysed as a function of device architecture. The special SOI parasitic phenomena,...The main electrical properties of advanced Silicon On Insulator MOSFETs are addressed. The subthreshold and high field operations are analysed as a function of device architecture. The special SOI parasitic phenomena, such as the floating body potential and temperature, are critically reviewed. The main limitations of submicron MOSFET are comparatively evaluated for various SOI structures. Short channel and hot carrier effects as well as the reliability of the SOI technology are investigated for gate length down to sub\|0 1 micron.展开更多
A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and D...A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.展开更多
Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end ...Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.展开更多
在集成电路设计领域,绝缘体上硅(SOI)工艺以其较小的寄生效应、更快的速度,得到广泛应用。但由于SOI工艺器件的结构特点及自加热效应(SHE)的影响,其静电放电(ESD)防护器件设计成为一大技术难点。当工艺进入深亚微米技术节点,基于部分耗...在集成电路设计领域,绝缘体上硅(SOI)工艺以其较小的寄生效应、更快的速度,得到广泛应用。但由于SOI工艺器件的结构特点及自加热效应(SHE)的影响,其静电放电(ESD)防护器件设计成为一大技术难点。当工艺进入深亚微米技术节点,基于部分耗尽型SOI(PD-SOI)工艺的ESD防护器件设计尤为困难。为了提高深亚微米SOI工艺电路的可靠性,开展了分析研究。结合SOI工艺器件的结构特点,针对性地进行了ESD防护器件选择,合理设计了器件尺寸参数,并优化设计了器件版图。使用该设计的一款数字电路,通过了4.5 k V人体模型(HBM)的ESD测试。该设计有效解决了深亚微米SOI工艺ESD防护器件稳健性弱的问题。展开更多
We investigate how F exposure impacts the hot-carrier degradation in deep submicron NMOSFET with different technologies and device geometries for the first time. The results show that hot-carrier degradations on irrad...We investigate how F exposure impacts the hot-carrier degradation in deep submicron NMOSFET with different technologies and device geometries for the first time. The results show that hot-carrier degradations on irradiated devices are greater than those without irradiation, especially for narrow channel device. The reason is attributed to charge traps in STI, which then induce different electric field and impact ionization rates during hotcarrier stress.展开更多
文摘The main electrical properties of advanced Silicon On Insulator MOSFETs are addressed. The subthreshold and high field operations are analysed as a function of device architecture. The special SOI parasitic phenomena, such as the floating body potential and temperature, are critically reviewed. The main limitations of submicron MOSFET are comparatively evaluated for various SOI structures. Short channel and hot carrier effects as well as the reliability of the SOI technology are investigated for gate length down to sub\|0 1 micron.
文摘A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.
基金supported by the National Natural Science Foundation of China (No.61006021)
文摘Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.
文摘在集成电路设计领域,绝缘体上硅(SOI)工艺以其较小的寄生效应、更快的速度,得到广泛应用。但由于SOI工艺器件的结构特点及自加热效应(SHE)的影响,其静电放电(ESD)防护器件设计成为一大技术难点。当工艺进入深亚微米技术节点,基于部分耗尽型SOI(PD-SOI)工艺的ESD防护器件设计尤为困难。为了提高深亚微米SOI工艺电路的可靠性,开展了分析研究。结合SOI工艺器件的结构特点,针对性地进行了ESD防护器件选择,合理设计了器件尺寸参数,并优化设计了器件版图。使用该设计的一款数字电路,通过了4.5 k V人体模型(HBM)的ESD测试。该设计有效解决了深亚微米SOI工艺ESD防护器件稳健性弱的问题。
文摘We investigate how F exposure impacts the hot-carrier degradation in deep submicron NMOSFET with different technologies and device geometries for the first time. The results show that hot-carrier degradations on irradiated devices are greater than those without irradiation, especially for narrow channel device. The reason is attributed to charge traps in STI, which then induce different electric field and impact ionization rates during hotcarrier stress.
