提出一种双通道16位串型数模转换器(Digital to Analog Converter,DAC)结构,该结构为电流舵与串电阻混合型DAC。设计采用4+6+6的分段方式,从结构角度能有效降低DAC的功耗,其中高4位采用串电阻型16选1的译码结构,中6位采用串电阻型64选1...提出一种双通道16位串型数模转换器(Digital to Analog Converter,DAC)结构,该结构为电流舵与串电阻混合型DAC。设计采用4+6+6的分段方式,从结构角度能有效降低DAC的功耗,其中高4位采用串电阻型16选1的译码结构,中6位采用串电阻型64选1的译码结构,低6位采用温度计电流舵译码结构。并利用Spectre工具仿真验证DAC的功能和性能。使用0.5μm CMOS工艺实现电路版图。在25℃环境温度下,仿真结果表明电流功耗为730μA,有效位数(ENOB)为15.19 bit,信噪比(SNR)为93.21 dB,总谐波失真(THD)为68.00 dB,无杂散动态范围(SFDR)为94.49 dB。展开更多
Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q;random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog conver...Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q;random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process.The total consumption is only 10 mW from a single 1.2-V power supply,and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively.When the output signal frequency is 1-5 MHz at 100-MSPS sampling rate,the SFDR is measured to be 70 dB.The die area is about 0.2 mm;.展开更多
A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by non...A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero（TRI-DRRZ）.Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.展开更多
Thelinearityofcurrent-steeringdigital-to-analogconverters（DACs）atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matchin...Thelinearityofcurrent-steeringdigital-to-analogconverters（DACs）atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range（SFDR） for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.展开更多
A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger out...A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.展开更多
This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure i...This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL ≤60.25 LSB, INL ≤6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm^2 in a 1P-8M 55 nm CMOS process.展开更多
A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compro...A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 #m CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which can perform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within 4-0.28 LSB and 4-0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 roW.展开更多
A 12-bit, 100-MHz CMOS current-steering D/A converter for CNC （computer number control） systems is presented. To reduce the glitch and increase the SFDR （spurious-free dynamic range）, a low crosspoint switch drive...A 12-bit, 100-MHz CMOS current-steering D/A converter for CNC （computer number control） systems is presented. To reduce the glitch and increase the SFDR （spurious-free dynamic range）, a low crosspoint switch driver and a special dummy switch are applied. In addition, a 4-5-3 segmental structure is used to optimize the performance and layout area. After improvement, the biggest glitch energy decreased from 6.7 pVs to 1.7 pVs, the INL decreased from 2 LSB to 0.8 LSB, the SFDR is 78 dB at a 100-MSPS clock rate and 1 MHz output frequency. This DAC can deliver up to 20.8 mA full-scale current into a 50 Ω load. The power when operating at full-scale current is 163 mW. The layout area is 1.8 × 1.8 mm2 in a standard 0.35-um CMOS technology.展开更多
文摘提出一种双通道16位串型数模转换器(Digital to Analog Converter,DAC)结构,该结构为电流舵与串电阻混合型DAC。设计采用4+6+6的分段方式,从结构角度能有效降低DAC的功耗,其中高4位采用串电阻型16选1的译码结构,中6位采用串电阻型64选1的译码结构,低6位采用温度计电流舵译码结构。并利用Spectre工具仿真验证DAC的功能和性能。使用0.5μm CMOS工艺实现电路版图。在25℃环境温度下,仿真结果表明电流功耗为730μA,有效位数(ENOB)为15.19 bit,信噪比(SNR)为93.21 dB,总谐波失真(THD)为68.00 dB,无杂散动态范围(SFDR)为94.49 dB。
文摘Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q;random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process.The total consumption is only 10 mW from a single 1.2-V power supply,and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively.When the output signal frequency is 1-5 MHz at 100-MSPS sampling rate,the SFDR is measured to be 70 dB.The die area is about 0.2 mm;.
基金supported by the National High Technology Research and Development Program of China(No.SS2013AA011203)the Specialized Research Fund for the Doctoral Program of Higher Education of China(No.20110002110058)
文摘A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero（TRI-DRRZ）.Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.
基金Project supported by the National Natural Science Foundation of China(Nos.60976024,61306029)the National High Technology Research and Development Program of China(No.2013AA014103)
文摘Thelinearityofcurrent-steeringdigital-to-analogconverters（DACs）atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range（SFDR） for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.
基金Project supported by the National Natural Science Foundation of China(Nos.61006027,61176030)the Research Foundation of Key Laboratory of Analog Integrated Circuit(Nos.9140C0902120C09034,9140c090204130c09042)the Fundamental Research Funds for the Central Universities of China(No.ZYGX2012J003)
文摘A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.
基金supported by the Major National Science&Technology Program of China(No.2012ZX03004004-002)
文摘This paper presents an 11-bit 160 MS/s 2-channel current-steering digital-to-analog converter（DAC）IP. The circuit and layout are carefully designed to optimize its performance and area. A 6-2-3 segmented structure is used for the trade-off among linearity, area and layout complexity. The sizes of current source transistors are calculated out according to the process matching parameter. The unary current cells are placed in a one-dimension distribution to simplify the layout routing, spare area and wiring layer. Their sequences are also carefully designed to reduce integral nonlinearity. The test result presents an SFDR of 72 dBc at 4.88 MHz input signal with DNL ≤60.25 LSB, INL ≤6 0.8 LSB. The full-scale output current is 5 m A with a 2.5 V analog power supply. The core of each channel occupies 0.08 mm^2 in a 1P-8M 55 nm CMOS process.
基金Project supported by the National Natural Science Foundation of China(No.61271331)the Jiangsu Provincial PAPD Program
文摘A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 #m CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which can perform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within 4-0.28 LSB and 4-0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 roW.
基金Project supported by the Hubei Natural Science Foundation of China(No.2010CDB02706)
文摘A 12-bit, 100-MHz CMOS current-steering D/A converter for CNC （computer number control） systems is presented. To reduce the glitch and increase the SFDR （spurious-free dynamic range）, a low crosspoint switch driver and a special dummy switch are applied. In addition, a 4-5-3 segmental structure is used to optimize the performance and layout area. After improvement, the biggest glitch energy decreased from 6.7 pVs to 1.7 pVs, the INL decreased from 2 LSB to 0.8 LSB, the SFDR is 78 dB at a 100-MSPS clock rate and 1 MHz output frequency. This DAC can deliver up to 20.8 mA full-scale current into a 50 Ω load. The power when operating at full-scale current is 163 mW. The layout area is 1.8 × 1.8 mm2 in a standard 0.35-um CMOS technology.
