New non-volatile memory (NVM)technologies are expected to replace main memory DRAM (dynamic random access memory)in the near future.NAND flash technological breakthroughs have enabled wide adoption of solid state driv...New non-volatile memory (NVM)technologies are expected to replace main memory DRAM (dynamic random access memory)in the near future.NAND flash technological breakthroughs have enabled wide adoption of solid state drives (SSDs)in storage systems.However,flash-based SSDs,by nature,cannot avoid low endurance problems because each cell only allows a limited number of erasures.This can give rise to critical SSD reliability issues.Since many SSD write operations eventually cause many SSD erase operations,reducing SSD write traffic plays a crucial role in SSD reliability. This paper proposes two NVM-based buffer cache policies which can work together in different layers to maximally reduce SSD write traffic:a main memory buffer cache design named Hierarchical Adaptive Replacement Cache (H-ARC)and an internal SSD write buffer design named Write Traffic Reduction Buffer (WRB).H-ARC considers four factors (dirty,clean, recency,and frequency)to reduce write traffic and improve cache hit ratios in the host.WRB reduces block erasures and write traffic further inside an SSD by effectively exploiting temporal and spatial localities.These two comprehensive schemes significantly reduce total SSD write traffic at each different layer (i.e.,host and SSD)by up to 3x.Consequently,they help extend SSD lifespan without system performance degradation.展开更多
This research proposes a phase-change memory （PCM） based main memory system with an effective combi- nation of a superblock-based adaptive buffering structure and its associated set divisible last-level cache （LLC...This research proposes a phase-change memory （PCM） based main memory system with an effective combi- nation of a superblock-based adaptive buffering structure and its associated set divisible last-level cache （LLC）. To achieve high performance similar to that of dynamic random-access memory （DRAM） based main memory, the superblock-based adaptive buffer （SABU） is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer （SBPB） and an adaptive sub-block reusing buffer （SBRB）, and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.展开更多
基于闪存的固态硬盘(solid state driver,简称SSD)已经广泛应用于各种移动设备、PC机和服务器.与磁盘相比,尽管SSD具有数据存取速度高、抗震、低功耗等优良特性,但SSD自身也存在读写不对称、价格昂贵等不利因素,这使得SSD短期内不会完...基于闪存的固态硬盘(solid state driver,简称SSD)已经广泛应用于各种移动设备、PC机和服务器.与磁盘相比,尽管SSD具有数据存取速度高、抗震、低功耗等优良特性,但SSD自身也存在读写不对称、价格昂贵等不利因素,这使得SSD短期内不会完全取代磁盘.将SSD和磁盘组合构建混合系统,可以发挥不同的硬件特性,提升系统性能.基于MLC型SSD和SLC型SSD之间的特性差异,提出了一种闪存敏感的多级缓存管理策略——FAMC.FAMC将SSD用在内存和磁盘之间作扩展缓存,针对数据库系统、文件管理中数据访问的特点,有选择地将内存牺牲页缓存到不同类型的SSD.FAMC同时考虑写请求模式和负载类型对系统性能的影响,设计实现对SSD友好的数据管理策略.此外,FAMC基于不同的数据置换代价提出了适用于SSD的缓冲区管理算法.基于多级缓存存储系统对FAMC的性能进行了评测,实验结果表明,FAMC可以大幅度降低系统响应时间,减少磁盘I/O.展开更多
文摘New non-volatile memory (NVM)technologies are expected to replace main memory DRAM (dynamic random access memory)in the near future.NAND flash technological breakthroughs have enabled wide adoption of solid state drives (SSDs)in storage systems.However,flash-based SSDs,by nature,cannot avoid low endurance problems because each cell only allows a limited number of erasures.This can give rise to critical SSD reliability issues.Since many SSD write operations eventually cause many SSD erase operations,reducing SSD write traffic plays a crucial role in SSD reliability. This paper proposes two NVM-based buffer cache policies which can work together in different layers to maximally reduce SSD write traffic:a main memory buffer cache design named Hierarchical Adaptive Replacement Cache (H-ARC)and an internal SSD write buffer design named Write Traffic Reduction Buffer (WRB).H-ARC considers four factors (dirty,clean, recency,and frequency)to reduce write traffic and improve cache hit ratios in the host.WRB reduces block erasures and write traffic further inside an SSD by effectively exploiting temporal and spatial localities.These two comprehensive schemes significantly reduce total SSD write traffic at each different layer (i.e.,host and SSD)by up to 3x.Consequently,they help extend SSD lifespan without system performance degradation.
文摘This research proposes a phase-change memory （PCM） based main memory system with an effective combi- nation of a superblock-based adaptive buffering structure and its associated set divisible last-level cache （LLC）. To achieve high performance similar to that of dynamic random-access memory （DRAM） based main memory, the superblock-based adaptive buffer （SABU） is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer （SBPB） and an adaptive sub-block reusing buffer （SBRB）, and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.
文摘基于闪存的固态硬盘(solid state driver,简称SSD)已经广泛应用于各种移动设备、PC机和服务器.与磁盘相比,尽管SSD具有数据存取速度高、抗震、低功耗等优良特性,但SSD自身也存在读写不对称、价格昂贵等不利因素,这使得SSD短期内不会完全取代磁盘.将SSD和磁盘组合构建混合系统,可以发挥不同的硬件特性,提升系统性能.基于MLC型SSD和SLC型SSD之间的特性差异,提出了一种闪存敏感的多级缓存管理策略——FAMC.FAMC将SSD用在内存和磁盘之间作扩展缓存,针对数据库系统、文件管理中数据访问的特点,有选择地将内存牺牲页缓存到不同类型的SSD.FAMC同时考虑写请求模式和负载类型对系统性能的影响,设计实现对SSD友好的数据管理策略.此外,FAMC基于不同的数据置换代价提出了适用于SSD的缓冲区管理算法.基于多级缓存存储系统对FAMC的性能进行了评测,实验结果表明,FAMC可以大幅度降低系统响应时间,减少磁盘I/O.
