A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-a...A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.展开更多
在增益增强型运算放大器优化中采用了自动设计方法,此方法在电路性能方程式和自适应遗传优化算法基础上对电路性能指标进行优化。该放大器在0.18μm CM O S工艺条件下中开环增益为92.1 dB,单位增益带宽积为1.78 GH z,相位裕度为55.1...在增益增强型运算放大器优化中采用了自动设计方法,此方法在电路性能方程式和自适应遗传优化算法基础上对电路性能指标进行优化。该放大器在0.18μm CM O S工艺条件下中开环增益为92.1 dB,单位增益带宽积为1.78 GH z,相位裕度为55.1°和0.2%建立时间为1.27 ns,同时说明此优化设计方法的有效性。展开更多
A 9.8–30.1 GHz CMOS low-noise amplifier(LNA)with a 3.2-dB minimum noise figure(NF)is presented.At the architecture level,a topology based on common-gate(CG)cascading with a common-source(CS)amplifier is proposed for ...A 9.8–30.1 GHz CMOS low-noise amplifier(LNA)with a 3.2-dB minimum noise figure(NF)is presented.At the architecture level,a topology based on common-gate(CG)cascading with a common-source(CS)amplifier is proposed for simultaneous wideband input matching and relatively high gain.At the circuit level,multiple techniques are proposed to improve LNA performance.First,in the CG stage,loading effect is properly used instead of the conventional feedback technique,to enable simultaneous impedance and noise matching.Second,based on in-depth theoretical analysis,the inductor-and transformer-based gm-boosting techniques are employed for the CG and CS stages,respectively,to enhance the gain and reduce power consumption.Third,the floating-body method,which was originally proposed to lower NF in CS amplifiers,is adopted in the CG stage to further reduce NF.Fabricated in a 65-nm CMOS technology,the LNA chip occupies an area of only 0.2 mm^(2)and measures a maximum power gain of 10.9 dB with−3 dB bandwidth from 9.8 to 30.1 GHz.The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth.The LNA consumes 15.6 mW from a 1.2-V supply.展开更多
基金supported by the National High Technology Research and Development Program of China(No.2002AA1Z1200)
文摘A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.
文摘在增益增强型运算放大器优化中采用了自动设计方法,此方法在电路性能方程式和自适应遗传优化算法基础上对电路性能指标进行优化。该放大器在0.18μm CM O S工艺条件下中开环增益为92.1 dB,单位增益带宽积为1.78 GH z,相位裕度为55.1°和0.2%建立时间为1.27 ns,同时说明此优化设计方法的有效性。
基金Project supported by the National Key R&D Program of China(No.2018YFB1802000)the Key-Area R&D Program of Guangdong Province,China(No.2018B010115001)the Guangdong Innovative and Entrepreneurial Research Team Program,China(No.2017ZT07X032)。
文摘A 9.8–30.1 GHz CMOS low-noise amplifier(LNA)with a 3.2-dB minimum noise figure(NF)is presented.At the architecture level,a topology based on common-gate(CG)cascading with a common-source(CS)amplifier is proposed for simultaneous wideband input matching and relatively high gain.At the circuit level,multiple techniques are proposed to improve LNA performance.First,in the CG stage,loading effect is properly used instead of the conventional feedback technique,to enable simultaneous impedance and noise matching.Second,based on in-depth theoretical analysis,the inductor-and transformer-based gm-boosting techniques are employed for the CG and CS stages,respectively,to enhance the gain and reduce power consumption.Third,the floating-body method,which was originally proposed to lower NF in CS amplifiers,is adopted in the CG stage to further reduce NF.Fabricated in a 65-nm CMOS technology,the LNA chip occupies an area of only 0.2 mm^(2)and measures a maximum power gain of 10.9 dB with−3 dB bandwidth from 9.8 to 30.1 GHz.The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth.The LNA consumes 15.6 mW from a 1.2-V supply.
