超大规模集成电路和超深亚微米技术的快速发展,促使了系统芯片(System on Chip,SoC)的产生,同时在SoC中也集成了越来越多的嵌入式存储器,因此嵌入式存储器对SoC芯片的整体性能有非常重要的影响;文章针对SoC中的嵌入式存储器的可测试性...超大规模集成电路和超深亚微米技术的快速发展,促使了系统芯片(System on Chip,SoC)的产生,同时在SoC中也集成了越来越多的嵌入式存储器,因此嵌入式存储器对SoC芯片的整体性能有非常重要的影响;文章针对SoC中的嵌入式存储器的可测试性设计展开研究;文章基于IEEE 1500标准针对DRAM和SRAM设计了具有兼容性的存储器的测试壳结构,并结合BIST控制器,在Quar-tusⅡ平台上,采用硬件描述语言对测试壳在不同测试指令下的有效性和灵活性进行验证,结果表明文章所设计的测试壳结构达到了预期的要求。展开更多
目前采用IEEE 1500测试外壳的方法可以一定程度上解决NoC(Netword on Chip)路由器测试的问题,但当测试外壳的旁路出现一个以上的故障时,很可能导致一整条扫描链上的NoC路由器测试失败.针对该问题,本文通过提出一个深度优先最短路径算法...目前采用IEEE 1500测试外壳的方法可以一定程度上解决NoC(Netword on Chip)路由器测试的问题,但当测试外壳的旁路出现一个以上的故障时,很可能导致一整条扫描链上的NoC路由器测试失败.针对该问题,本文通过提出一个深度优先最短路径算法得到从固定的扫描输入端到扫描输出端的最短路径,并通过提出的递归划分逐步求精法对路径进行筛选分块排序,构造多条扫描测试链将整个网络中的路由器分开测试.本文给出了测试外壳旁路故障的诊断和容错方法,使用节点分类测试方法实现对NoC路由器旁路故障的定位,并通过本文提出的测试外壳结构实现对故障旁路的容错.展开更多
Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-sca...Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional （3D） integration has been proposed to sustain Moore＇s law by incorporating through-silicon vias （TSVs） to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on- Chips （SoCs）. Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and展开更多
文摘超大规模集成电路和超深亚微米技术的快速发展,促使了系统芯片(System on Chip,SoC)的产生,同时在SoC中也集成了越来越多的嵌入式存储器,因此嵌入式存储器对SoC芯片的整体性能有非常重要的影响;文章针对SoC中的嵌入式存储器的可测试性设计展开研究;文章基于IEEE 1500标准针对DRAM和SRAM设计了具有兼容性的存储器的测试壳结构,并结合BIST控制器,在Quar-tusⅡ平台上,采用硬件描述语言对测试壳在不同测试指令下的有效性和灵活性进行验证,结果表明文章所设计的测试壳结构达到了预期的要求。
文摘目前采用IEEE 1500测试外壳的方法可以一定程度上解决NoC(Netword on Chip)路由器测试的问题,但当测试外壳的旁路出现一个以上的故障时,很可能导致一整条扫描链上的NoC路由器测试失败.针对该问题,本文通过提出一个深度优先最短路径算法得到从固定的扫描输入端到扫描输出端的最短路径,并通过提出的递归划分逐步求精法对路径进行筛选分块排序,构造多条扫描测试链将整个网络中的路由器分开测试.本文给出了测试外壳旁路故障的诊断和容错方法,使用节点分类测试方法实现对NoC路由器旁路故障的定位,并通过本文提出的测试外壳结构实现对故障旁路的容错.
基金This work was supported in part by the National Basic Research 973 Program of China under Grant No. 2011CB302503 and the National Natural Science Foundation of China under Grant Nos. 60806014, 61076037, 60906018, 61173006, 60921002, 60831160526.
文摘Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional （3D） integration has been proposed to sustain Moore＇s law by incorporating through-silicon vias （TSVs） to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on- Chips （SoCs）. Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and
