Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid developme...Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.展开更多
The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical ...The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical quantities,ICs typically provide functionalities related to the signals of these transducers,such as analog-to-digital conversion,amplification,filtering and information processing as well as communication between the MEMS transducer and the outside world.Thus,the vast majority of commercial MEMS products,such as accelerometers,gyroscopes and micro-mirror arrays,are integrated and packaged together with ICs.There are a variety of possible methods of integrating and packaging MEMS and IC components,and the technology of choice strongly depends on the device,the field of application and the commercial requirements.In this review paper,traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed.These include approaches based on the hybrid integration of multiple chips(multi-chip solutions)as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.These are important technological building blocks for the‘More-Than-Moore’paradigm described in the International Technology Roadmap for Semiconductors.In this paper,the various approaches are categorized in a coherent manner,their merits are discussed,and suitable application areas and implementations are critically investigated.The implications of the different MEMS and IC integration approaches for packaging,testing and final system costs are reviewed.展开更多
该文提出一种基于权重与轮询(Round-Robin,RR)的双层仲裁算法,在无冲突和多冲突情况下分别采用改进的固定优先级(Fixed Priority,FP)和RR仲裁轮流工作,并通过彩票项设置权重。在非空非抢占(NonIdling and NonPreemptive,NINP)模型下相...该文提出一种基于权重与轮询(Round-Robin,RR)的双层仲裁算法,在无冲突和多冲突情况下分别采用改进的固定优先级(Fixed Priority,FP)和RR仲裁轮流工作,并通过彩票项设置权重。在非空非抢占(NonIdling and NonPreemptive,NINP)模型下相比传统FP,RR和Lottery仲裁算法有更好的输出带宽比、带宽占用率和功耗,在速度和面积上有一定优势。该算法适应多种请求环境,逻辑简单,容易实现,可应用于总线结构的片上系统(System-on-Chip,SoC)。展开更多
提出一种片上网络(NoC)拓扑结构——Spidernet,并对其网络的主要属性如节点度、网络直径、连通度、平均最短路径和平均最短布线等进行了研究。首先将 Spidernet 与其它拓扑结构的属性进行比较,并采用模拟退火的布局映射算法,根据NoC的...提出一种片上网络(NoC)拓扑结构——Spidernet,并对其网络的主要属性如节点度、网络直径、连通度、平均最短路径和平均最短布线等进行了研究。首先将 Spidernet 与其它拓扑结构的属性进行比较,并采用模拟退火的布局映射算法,根据NoC的布局结构,将不同的节点放入 NoC 网格中,即给出一组被绑定和调度的可供选择 IP 核,在满足 IP 核所占用芯片面积的条件下将选择的 IP 核映射到网络中,目标是最小化平均布线长度。网络拓扑结构图描述文件和 IP 核任务图作为输入。实验中运行基准程序,结果表明提出的网络拓扑结构更适合于将来的 SoC 的片上网络构造。展开更多
基金Supported by National Natural Science Foundation of China(No.61271149)National High Technology Research and Development Program of China(No.2012AA-012301)National Science and Technology Major Project of China(No.2013ZX03006004)
文摘Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.
基金The work was partially funded by the Swedish Research Council,by the European 7^(th)Framework Programme under grant agreement FP7-NEMIAC(No.288670)by the European Research Council through the ERC Advanced Grant xMEMs(No.267528)and the ERC Starting Grant M&M’s(No.277879).
文摘The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical quantities,ICs typically provide functionalities related to the signals of these transducers,such as analog-to-digital conversion,amplification,filtering and information processing as well as communication between the MEMS transducer and the outside world.Thus,the vast majority of commercial MEMS products,such as accelerometers,gyroscopes and micro-mirror arrays,are integrated and packaged together with ICs.There are a variety of possible methods of integrating and packaging MEMS and IC components,and the technology of choice strongly depends on the device,the field of application and the commercial requirements.In this review paper,traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed.These include approaches based on the hybrid integration of multiple chips(multi-chip solutions)as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.These are important technological building blocks for the‘More-Than-Moore’paradigm described in the International Technology Roadmap for Semiconductors.In this paper,the various approaches are categorized in a coherent manner,their merits are discussed,and suitable application areas and implementations are critically investigated.The implications of the different MEMS and IC integration approaches for packaging,testing and final system costs are reviewed.
文摘该文提出一种基于权重与轮询(Round-Robin,RR)的双层仲裁算法,在无冲突和多冲突情况下分别采用改进的固定优先级(Fixed Priority,FP)和RR仲裁轮流工作,并通过彩票项设置权重。在非空非抢占(NonIdling and NonPreemptive,NINP)模型下相比传统FP,RR和Lottery仲裁算法有更好的输出带宽比、带宽占用率和功耗,在速度和面积上有一定优势。该算法适应多种请求环境,逻辑简单,容易实现,可应用于总线结构的片上系统(System-on-Chip,SoC)。
文摘提出一种片上网络(NoC)拓扑结构——Spidernet,并对其网络的主要属性如节点度、网络直径、连通度、平均最短路径和平均最短布线等进行了研究。首先将 Spidernet 与其它拓扑结构的属性进行比较,并采用模拟退火的布局映射算法,根据NoC的布局结构,将不同的节点放入 NoC 网格中,即给出一组被绑定和调度的可供选择 IP 核,在满足 IP 核所占用芯片面积的条件下将选择的 IP 核映射到网络中,目标是最小化平均布线长度。网络拓扑结构图描述文件和 IP 核任务图作为输入。实验中运行基准程序,结果表明提出的网络拓扑结构更适合于将来的 SoC 的片上网络构造。
