A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct currentmode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its perfor...A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct currentmode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 #A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%.展开更多
A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel acce...A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...展开更多
基于SMIC 0.35μm嵌入式EEPROM工艺实现了一款256byte的超低功耗EEPROM IP核。典型情况下,读电流为40μA,页编程电流为250μA,特别适合RFID(Radio Frequency Identification)标签芯片的应用。针对芯片中各种功耗的来源进行了详细的分析...基于SMIC 0.35μm嵌入式EEPROM工艺实现了一款256byte的超低功耗EEPROM IP核。典型情况下,读电流为40μA,页编程电流为250μA,特别适合RFID(Radio Frequency Identification)标签芯片的应用。针对芯片中各种功耗的来源进行了详细的分析,并给出了相应的实现方法。展开更多
Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a...Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.展开更多
This paper presents a sense amplifier scheme for low-voltage embedded flash （eFlash） memory applications. The topology of the sense amplifier is based on current mode comparison. Moreover, an offset-voltage eliminat...This paper presents a sense amplifier scheme for low-voltage embedded flash （eFlash） memory applications. The topology of the sense amplifier is based on current mode comparison. Moreover, an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current. The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process, and the sense time is 0.43 ns at 1.5 V, corresponding to a 46% improvement over the conventional technologies.展开更多
文摘A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct currentmode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 #A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%.
文摘A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...
文摘基于SMIC 0.35μm嵌入式EEPROM工艺实现了一款256byte的超低功耗EEPROM IP核。典型情况下,读电流为40μA,页编程电流为250μA,特别适合RFID(Radio Frequency Identification)标签芯片的应用。针对芯片中各种功耗的来源进行了详细的分析,并给出了相应的实现方法。
基金Research General Direction funded this research at Universidad Santiago de Cali,Grant Number 01-2021 and APC was funded by 01-2021.
文摘Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.
基金Project supported by the National High Technology Research and Development Program of China(No.2008AA031403)the National Basic Research Program of China(No.2010CB934204)the National Science Fund for Distinguished Young Scholars of China (No.60825403)
文摘This paper presents a sense amplifier scheme for low-voltage embedded flash （eFlash） memory applications. The topology of the sense amplifier is based on current mode comparison. Moreover, an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current. The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process, and the sense time is 0.43 ns at 1.5 V, corresponding to a 46% improvement over the conventional technologies.
