摘要
设计了一种静态随机读写存储器(SRAM)的BiCMOS存储单元及其外围电路。HSpice仿真结果表明,所设计的SRAM电路的电源电压可低于3V以下,它既保留了CMOSSRAM低功耗、高集成度的特征,又获得了双极型电路快速、大电流驱动能力的长处,因而特别适用于高速缓冲静态存储器和便携式数字电子设备的存储系统中。
A new highperformance SRAM cell and its peripheral circuits, such as sense amplifier, address decoder, I/O circuit and so on, are designed in this paper HSpice simulation results show that the designed BiCMOS SRAM can operate down to sub3V This BiCMOS SRAM circuit has not only the features of low power dissipation and high integration density of CMOS SRAM, but also the advantages of highspeed and powerful driving capability Therefore, it is very suitable for cache static random access memory and other handheld digital equipments
出处
《微电子学》
CAS
CSCD
北大核心
2003年第1期49-52,共4页
Microelectronics
基金
江苏省教育厅自然科学研究基金项目(02KJB510005)
江苏大学2001年青年基金项目(JDQ2001010)
徐州建筑职业技术学院2001年科研项目资助
