A thiocyanate ion selective poly(aniline) solid contact electrode based on manganese complex of N,N’-bis-(4-phenylazosalicylidene)-o-phenylene diamine ionophore was successfully developed. The electrode exhibits a go...A thiocyanate ion selective poly(aniline) solid contact electrode based on manganese complex of N,N’-bis-(4-phenylazosalicylidene)-o-phenylene diamine ionophore was successfully developed. The electrode exhibits a good linear response of 58.1 mV/decade (at 20?C ± 0.2?C, r2 = 0.998) with in the concentration range of 1 × 10–1.0 ~ 1 × 10–5.8 M thiocyanate solution. The composition of this electrode was: ionophore 0.040, polyvinylchloride 0.300, dibutylphthalate 0.660 (mass). This dibutylphthalate plasticizer provides the best response characteristics. The electrode shows good selectivity for thiocyanate ion in comparison with any other anions and is suitable for use with aqueous solutions of pH 4.0 ~ 6.0. The standard deviations of the measured emf difference were ±1.70 and ±2.01 mV for thiocyanate sample solutions of 1.0 × 10–2 M and 1.0 × 10–3 M, respectively. The stabilization time was less than 170 sec. and response time was less than 17 sec.展开更多
Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short c...Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects （SCEs）, leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SO1 FinFET is one of the best multigate structures that has gained importance in all electronic design automation （EDA） industries due to its improved short channel effects （SCEs）, because of its more effective gate-controlling capabilities. In this paper, our aim is to ex- plore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evalu- ated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope （SS）, ON current （Ion）, OFF current （/off） and Ion/loll ratio. The potential benefits of SOl FinFET at drain-to-source voltage, liDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain （Av）, output conductance （go）, trans-conductance （gin）, gate capacitance （Cgg）, and cut-off frequency OCT = gm/2πCgg） with spacer region variations.展开更多
Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET ...Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs(short channel effects) in sub22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2(conventional Hf02 spacer SOI FinFET) and device-D3(source/drain extended Hf02 spacer SOI FinFET) over the device-D1(conventional Si3 N4 spacer SOI FinFET) at 20 nm technology node through the 3-D(dimensional) simulation process. The major performance parameters like I(ON current), I(OFF current), gm(transconductance), gd(output conductance), A(intrinsic gain), SS(sub-threshold slope), TGF = g/I(trans-conductance generation factor), VEA(early voltage), GTFP(gain trans-conductance frequency product), TFP(tansconductance frequency product), GFP(gain frequency product), and f(cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation,device-D3 and D2 give better results in terms of gm, ID(drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f, GTFP, TFP, and GFP parameters both at low and high values of V=0.05 V and V=0.7 V respectively.展开更多
We propose a reliable asymmetric dual-k spacer with SiC source/drain（S/D）pocket as a stressor for a Si channel.This enhances the device performance in terms of electron mobility（eMobility）,current driving capabili...We propose a reliable asymmetric dual-k spacer with SiC source/drain（S/D）pocket as a stressor for a Si channel.This enhances the device performance in terms of electron mobility（eMobility）,current driving capabilities,transconductance（G_m）and subthreshold slope（SS）.The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance.We analysed the variation in drive current for different values of carbon（C）mole fraction y in Si_（1-y）C_y.It is found that the mole fraction also helps to improve device lifetime,performance enhancement also pointed by transconductance variation with the gate length.All the simulations are performed in the 3-D Sentaurus TCAD tool.The proposed device structure achieved ION=2.17 mA/μm for Si_（0.3）C_（0.7） and found that Si_（0.5）C_（0.5） is more suitable for the perspective of a process variation effect for 14 nm as the gate length.We introduce reliability issues and their solutions for Si（1-y）Cy FinFET for the first time.展开更多
In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presen...In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional（2D） Poisson＇s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model＇s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters,including the dielectric constant of gate-dielectric material.展开更多
Different channel lengths and layouts on 0.18μm NMOS transistors are designed for investigating the dependence of short channel effects(SCEs)on the width of shallow trench isolation(STI)devices and designing in radia...Different channel lengths and layouts on 0.18μm NMOS transistors are designed for investigating the dependence of short channel effects(SCEs)on the width of shallow trench isolation(STI)devices and designing in radiation hardness.Results show that,prior to irradiation,the devices exhibited near–ideal I–V characteristics,with no significant SCEs.Following irradiation,no noticeable shift of threshold voltage is observed,radiation–induced edge–leakage current,however,exhibits significant sensitivity on TID.Moreover,radiation–enhanced drain induced barrier lowering(DIBL)and channel length modulation(CLM)effects are observed on short–channel NMOS transistors.Comparing to stripe–gate layout,enclosed–gate layout has excellent radiation tolerance.展开更多
This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack chan...This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.展开更多
Using the semi-insulating property and small lattice constant a of wurtzite BGaN alloy, we propose a BGaN buffer with a B-content of 1% to enhance two-dimensional electron gas(2 DEG) confinement in a short-gate AlGaN/...Using the semi-insulating property and small lattice constant a of wurtzite BGaN alloy, we propose a BGaN buffer with a B-content of 1% to enhance two-dimensional electron gas(2 DEG) confinement in a short-gate AlGaN/GaN highelectron mobility transistor(HEMT). Based on the two-dimensional TCAD simulation, the direct current(DC) and radio frequency(RF) characteristics of the AlGaN/GaN/B_(0.01)Ga_(0.99)N structure HEMTs are theoretically studied. Our results show that the BGaN buffer device achieves good pinch-off quality and improves RF performance compared with GaN buffer device. The BGaN buffer device can allow a good immunity to shift of threshold voltage for the aspect ratio(LG/d)down to 6, which is much lower than that the GaN buffer device with L_G/d=11 can reach. Furthermore, due to a similar manner of enhancing 2 DEG confinement, the B_(0.01)Ga_(0.99)N buffer device has similar DC and RF characteristics to those the AlGaN buffer device possesses, and its ability to control short-channel effects(SCEs) is comparable to that of an Al_(0.03)Ga_(0.97)N buffer. Therefore, this BGaN buffer with very small B-content promises to be a new method to suppress SCEs in GaN HEMTs.展开更多
随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了...随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。展开更多
文摘A thiocyanate ion selective poly(aniline) solid contact electrode based on manganese complex of N,N’-bis-(4-phenylazosalicylidene)-o-phenylene diamine ionophore was successfully developed. The electrode exhibits a good linear response of 58.1 mV/decade (at 20?C ± 0.2?C, r2 = 0.998) with in the concentration range of 1 × 10–1.0 ~ 1 × 10–5.8 M thiocyanate solution. The composition of this electrode was: ionophore 0.040, polyvinylchloride 0.300, dibutylphthalate 0.660 (mass). This dibutylphthalate plasticizer provides the best response characteristics. The electrode shows good selectivity for thiocyanate ion in comparison with any other anions and is suitable for use with aqueous solutions of pH 4.0 ~ 6.0. The standard deviations of the measured emf difference were ±1.70 and ±2.01 mV for thiocyanate sample solutions of 1.0 × 10–2 M and 1.0 × 10–3 M, respectively. The stabilization time was less than 170 sec. and response time was less than 17 sec.
文摘Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects （SCEs）, leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SO1 FinFET is one of the best multigate structures that has gained importance in all electronic design automation （EDA） industries due to its improved short channel effects （SCEs）, because of its more effective gate-controlling capabilities. In this paper, our aim is to ex- plore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evalu- ated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope （SS）, ON current （Ion）, OFF current （/off） and Ion/loll ratio. The potential benefits of SOl FinFET at drain-to-source voltage, liDS = 0.05 V and VDS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain （Av）, output conductance （go）, trans-conductance （gin）, gate capacitance （Cgg）, and cut-off frequency OCT = gm/2πCgg） with spacer region variations.
文摘Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs(short channel effects) in sub22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2(conventional Hf02 spacer SOI FinFET) and device-D3(source/drain extended Hf02 spacer SOI FinFET) over the device-D1(conventional Si3 N4 spacer SOI FinFET) at 20 nm technology node through the 3-D(dimensional) simulation process. The major performance parameters like I(ON current), I(OFF current), gm(transconductance), gd(output conductance), A(intrinsic gain), SS(sub-threshold slope), TGF = g/I(trans-conductance generation factor), VEA(early voltage), GTFP(gain trans-conductance frequency product), TFP(tansconductance frequency product), GFP(gain frequency product), and f(cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation,device-D3 and D2 give better results in terms of gm, ID(drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f, GTFP, TFP, and GFP parameters both at low and high values of V=0.05 V and V=0.7 V respectively.
基金the M.P.Council of Science & Technology,Bhopal,India,for financial support under the R&D project scheme No:1950/CST/R&D/Phy & Engg Sc/2015:27~(th) Aug 2015
文摘We propose a reliable asymmetric dual-k spacer with SiC source/drain（S/D）pocket as a stressor for a Si channel.This enhances the device performance in terms of electron mobility（eMobility）,current driving capabilities,transconductance（G_m）and subthreshold slope（SS）.The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance.We analysed the variation in drive current for different values of carbon（C）mole fraction y in Si_（1-y）C_y.It is found that the mole fraction also helps to improve device lifetime,performance enhancement also pointed by transconductance variation with the gate length.All the simulations are performed in the 3-D Sentaurus TCAD tool.The proposed device structure achieved ION=2.17 mA/μm for Si_（0.3）C_（0.7） and found that Si_（0.5）C_（0.5） is more suitable for the perspective of a process variation effect for 14 nm as the gate length.We introduce reliability issues and their solutions for Si（1-y）Cy FinFET for the first time.
基金supported by the Science and Engineering Research Board(SERB),Department of Science and Technology,Ministry of Human Resource and Development,Government of India under Young Scientist Research(Grant No.SB/FTP/ETA-415/2012)
文摘In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional（2D） Poisson＇s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model＇s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters,including the dielectric constant of gate-dielectric material.
基金Supported by National Laboratory Analog Integrated Circuit Foundation(No.9140C090402110C0906)
文摘Different channel lengths and layouts on 0.18μm NMOS transistors are designed for investigating the dependence of short channel effects(SCEs)on the width of shallow trench isolation(STI)devices and designing in radiation hardness.Results show that,prior to irradiation,the devices exhibited near–ideal I–V characteristics,with no significant SCEs.Following irradiation,no noticeable shift of threshold voltage is observed,radiation–induced edge–leakage current,however,exhibits significant sensitivity on TID.Moreover,radiation–enhanced drain induced barrier lowering(DIBL)and channel length modulation(CLM)effects are observed on short–channel NMOS transistors.Comparing to stripe–gate layout,enclosed–gate layout has excellent radiation tolerance.
文摘This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.
基金Project supported by the Foundation Project of the Science and Technology on Electro-Optical Information Security Control Laboratory,China(Grant No.614210701041705)
文摘Using the semi-insulating property and small lattice constant a of wurtzite BGaN alloy, we propose a BGaN buffer with a B-content of 1% to enhance two-dimensional electron gas(2 DEG) confinement in a short-gate AlGaN/GaN highelectron mobility transistor(HEMT). Based on the two-dimensional TCAD simulation, the direct current(DC) and radio frequency(RF) characteristics of the AlGaN/GaN/B_(0.01)Ga_(0.99)N structure HEMTs are theoretically studied. Our results show that the BGaN buffer device achieves good pinch-off quality and improves RF performance compared with GaN buffer device. The BGaN buffer device can allow a good immunity to shift of threshold voltage for the aspect ratio(LG/d)down to 6, which is much lower than that the GaN buffer device with L_G/d=11 can reach. Furthermore, due to a similar manner of enhancing 2 DEG confinement, the B_(0.01)Ga_(0.99)N buffer device has similar DC and RF characteristics to those the AlGaN buffer device possesses, and its ability to control short-channel effects(SCEs) is comparable to that of an Al_(0.03)Ga_(0.97)N buffer. Therefore, this BGaN buffer with very small B-content promises to be a new method to suppress SCEs in GaN HEMTs.
文摘随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。
