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Analysis and performance exploration of high performance(HfO_2) SOI FinFETs over the conventional(Si_3N_4) SOI FinFET towards analog/RF design

Analysis and performance exploration of high performance(HfO_2) SOI FinFETs over the conventional(Si_3N_4) SOI FinFET towards analog/RF design
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摘要 Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs(short channel effects) in sub22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2(conventional Hf02 spacer SOI FinFET) and device-D3(source/drain extended Hf02 spacer SOI FinFET) over the device-D1(conventional Si3 N4 spacer SOI FinFET) at 20 nm technology node through the 3-D(dimensional) simulation process. The major performance parameters like I(ON current), I(OFF current), gm(transconductance), gd(output conductance), A(intrinsic gain), SS(sub-threshold slope), TGF = g/I(trans-conductance generation factor), VEA(early voltage), GTFP(gain trans-conductance frequency product), TFP(tansconductance frequency product), GFP(gain frequency product), and f(cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation,device-D3 and D2 give better results in terms of gm, ID(drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f, GTFP, TFP, and GFP parameters both at low and high values of V=0.05 V and V=0.7 V respectively. Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs(short channel effects) in sub22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2(conventional Hf02 spacer SOI FinFET) and device-D3(source/drain extended Hf02 spacer SOI FinFET) over the device-D1(conventional Si3 N4 spacer SOI FinFET) at 20 nm technology node through the 3-D(dimensional) simulation process. The major performance parameters like I_(on)(ON current), I_(off)(OFF current), gm(transconductance), gd(output conductance), A_V(intrinsic gain), SS(sub-threshold slope), TGF = g_m/I_d(trans-conductance generation factor), VEA(early voltage), GTFP(gain trans-conductance frequency product), TFP(tansconductance frequency product), GFP(gain frequency product), and f_T(cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation,device-D3 and D2 give better results in terms of gm, ID(drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f_T, GTFP, TFP, and GFP parameters both at low and high values of V_(DS)=0.05 V and V_(DS)=0.7 V respectively.
机构地区 VLSI Design Lab
出处 《Journal of Semiconductors》 EI CAS CSCD 2018年第12期68-74,共7页 半导体学报(英文版)
关键词 SOI FinFET SCEs intrinsic gain trans-conductance cut-off frequency SOI FinFET SCEs intrinsic gain trans-conductance cut-off frequency
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