This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diago...This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.展开更多
The problem of improving the performance of min-sum decoding of low-density parity-check （LDPC） codes is considered in this paper. Based on min-sum algorithm, a novel modified min-sum decoding algorithm for LDPC cod...The problem of improving the performance of min-sum decoding of low-density parity-check （LDPC） codes is considered in this paper. Based on min-sum algorithm, a novel modified min-sum decoding algorithm for LDPC codes is proposed. The proposed algorithm modifies the variable node message in the iteration process by averaging the new message and previous message if their signs are different. Compared with the standard min-sum algorithm, the modification is achieved with only a small increase in complexity, but significantly improves decoding performance for both regular and irregular LDPC codes. Simulation results show that the performance of our modified decoding algorithm is very close to that of the standard sum-product algorithm for moderate length LDPC codes.展开更多
In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC...In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.展开更多
In this paper, two-dimensional (2-D) correction scheme is proposed to improve the performance of conventional Min-Sum (MS) decoding of regular low density parity check codes. The adopted algorithm to obtain the correc...In this paper, two-dimensional (2-D) correction scheme is proposed to improve the performance of conventional Min-Sum (MS) decoding of regular low density parity check codes. The adopted algorithm to obtain the correction factors is simply based on estimating the mean square difference (MSD) between the transmitted codeword and the posteriori information of both bit and check node that produced at the MS decoder. Semi-practical tests using software-defined radio (SDR) and specific code simulations show that the proposed quasi-optimal algorithm provides a comparable error performance as Sum-Product (SP) decoding while requiring less complexity.展开更多
LDPC码是一种具有稀疏性且接近香农极限的线性分组码。目前被广泛应用的LDPC简化算法的译码性能损失较多,译码性能和复杂度折中的算法具有重要价值。对几种已知的译码算法进行了深入研究,提出一种基于变量节点更新改进的最小和算法,该...LDPC码是一种具有稀疏性且接近香农极限的线性分组码。目前被广泛应用的LDPC简化算法的译码性能损失较多,译码性能和复杂度折中的算法具有重要价值。对几种已知的译码算法进行了深入研究,提出一种基于变量节点更新改进的最小和算法,该算法与最小和算法、归一化最小和算法复杂度相当,但译码性能得到约0.5 d B和0.2 d B的提高,在中高信噪比区,更加接近LLR-BP算法的性能。展开更多
Non-binary low density parity check （NB-LDPC） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are requi...Non-binary low density parity check （NB-LDPC） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are required. They have better burst error correcting performance, especially with high order Galois fields （GF）. A shared comparator （SCOMP） architecture for elementary of check node （ECN）/elementary of variable node （EVN） to reduce decoder complexity is introduced because high complexity of check node （CN） and variable node （VN） prevent NB-LDPC decoder from widely applications. The decoder over GF（16） is based on the extended rain-sum （EMS） algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency, the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when SCOMP architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF（64） or GF（256）. Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications.展开更多
In this paper, we propose to generalize the coding schemes first proposed by Kozic &al to high spectral efficient modulation schemes. We study at first Chaos Coded Modulation based on the use of small ...In this paper, we propose to generalize the coding schemes first proposed by Kozic &al to high spectral efficient modulation schemes. We study at first Chaos Coded Modulation based on the use of small dimensional modulo-MAP encoding process and we give a solution to study the distance spectrum of such coding schemes to accurately predict their performances. However, the obtained performances are quite poor. To improve them, we use then a high dimensional modulo-MAP mapping process similar to the low-density generator-matrix codes (LDGM) introduced by Kozic &al. The main difference with their work is that we use an encoding and decoding process on GF (2m) which enables to obtain better performances while preserving a quite simple decoding algorithm when we use the Extended Min-Sum (EMS) algorithm of Declercq &Fossorier.展开更多
The complexity/performance balanced decoder for low-density parity-check （LDPC） codes is preferred in practical wireless communication systems. A low complexity LDPC decoder for the Consultative Committee for Space ...The complexity/performance balanced decoder for low-density parity-check （LDPC） codes is preferred in practical wireless communication systems. A low complexity LDPC decoder for the Consultative Committee for Space Data Systems （CCSDS） standard is achieved in DSP. An ap- proximate decoding algorithm, normalized rain-sum algorithm, is used in the implementation for its low amounts of computation. To reduce the performance loss caused by the approximation, the pa- rameters of the normalized min-sum algorithm are determined by calculating and finding the mini- mum value of thresholds through density evolution. The minimum value which indicates the best per- formance of the decoding algorithm is corresponding with the optimized parameters. In implementa- tion, the memory cost is saved by decomposing the parity-check matrix into submatrices to store and the computation of passing message in decoding is accelerated by using the intrinsic function of DSP. The performance of the decoder with optimized factors is simulated and compared with the ideal BP decoder. The result shows they have about the same performance.展开更多
为了降低低密度奇偶校验(Low Density Parity Check,LDPC)码的译码算法复杂度,提高译码性能,结合基于残余值的动态译码NW-RBP算法和最小和算法,提出了一种基于子迭代次数的改进NW-RBP算法,将此算法称为NW-RBPF算法。该算法在进行残余值...为了降低低密度奇偶校验(Low Density Parity Check,LDPC)码的译码算法复杂度,提高译码性能,结合基于残余值的动态译码NW-RBP算法和最小和算法,提出了一种基于子迭代次数的改进NW-RBP算法,将此算法称为NW-RBPF算法。该算法在进行残余值计算时利用最小和进行计算,并且根据子迭代过程中每行迭代更新的次数,由仿真得出的收敛因子计算对残余值的补偿值。仿真结果表明,该算法的译码性能相比NW-RBP算法提高了0.05 dB,收敛速度提高了1.5倍,并且其贪婪性降低,是一种适用于LDPC码,且译码性能良好、实现复杂度较低的译码算法。展开更多
This paper describes a coded cooperative multiple-input multiple-output(MIMO) scheme,where structured low-density parity-check(LDPC) codes belonging to a family of repeat-accumulate(RA) codes are employed.The outage p...This paper describes a coded cooperative multiple-input multiple-output(MIMO) scheme,where structured low-density parity-check(LDPC) codes belonging to a family of repeat-accumulate(RA) codes are employed.The outage probability of the scheme over Rayleigh fading channels is deduced.In an unknown channel state information(CSI) scenario,adaptive transversal filters based on a spatio-temporal recursive least squares(ST-RLS) algorithm are adopted in the destination to realize receive diversity gain.Also,a joint 'Min-Sum' iterative decoding is effectively carried out in the destination.Such a decoding algorithm agrees with the bilayer Tanner graph that can be used to fully characterize two distinct structured LDPC codes employed by the source and relay.Simulation results verify the effectiveness of the adopted filter in the coded cooperative MIMO scheme.Theoretical analysis and numerical simulations show that the LDPC coded cooperative MIMO scheme can well combine cooperation diversity,multi-receive diversity,and channel coding gains,and clearly outperforms coded noncooperation schemes under the same conditions.展开更多
基金supported by the National Natural Science Foundation of China(11705191)the Anhui Provincial Natural Science Foundation(1808085QF180)the Natural Science Foundation of Shanghai(18ZR1443600)
文摘This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.
基金supported by the Major State Basic Research Development Program of China (2009CB320300)
文摘The problem of improving the performance of min-sum decoding of low-density parity-check （LDPC） codes is considered in this paper. Based on min-sum algorithm, a novel modified min-sum decoding algorithm for LDPC codes is proposed. The proposed algorithm modifies the variable node message in the iteration process by averaging the new message and previous message if their signs are different. Compared with the standard min-sum algorithm, the modification is achieved with only a small increase in complexity, but significantly improves decoding performance for both regular and irregular LDPC codes. Simulation results show that the performance of our modified decoding algorithm is very close to that of the standard sum-product algorithm for moderate length LDPC codes.
文摘In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.
文摘In this paper, two-dimensional (2-D) correction scheme is proposed to improve the performance of conventional Min-Sum (MS) decoding of regular low density parity check codes. The adopted algorithm to obtain the correction factors is simply based on estimating the mean square difference (MSD) between the transmitted codeword and the posteriori information of both bit and check node that produced at the MS decoder. Semi-practical tests using software-defined radio (SDR) and specific code simulations show that the proposed quasi-optimal algorithm provides a comparable error performance as Sum-Product (SP) decoding while requiring less complexity.
文摘LDPC码是一种具有稀疏性且接近香农极限的线性分组码。目前被广泛应用的LDPC简化算法的译码性能损失较多,译码性能和复杂度折中的算法具有重要价值。对几种已知的译码算法进行了深入研究,提出一种基于变量节点更新改进的最小和算法,该算法与最小和算法、归一化最小和算法复杂度相当,但译码性能得到约0.5 d B和0.2 d B的提高,在中高信噪比区,更加接近LLR-BP算法的性能。
基金supported by the Foundation of the Chinese Academy of Sciences (KGFZD-135-16-015)
文摘Non-binary low density parity check （NB-LDPC） codes are considered as preferred candidate in conditions where short/medium codeword length codes and better performance at low signal to noise ratios （SNR） are required. They have better burst error correcting performance, especially with high order Galois fields （GF）. A shared comparator （SCOMP） architecture for elementary of check node （ECN）/elementary of variable node （EVN） to reduce decoder complexity is introduced because high complexity of check node （CN） and variable node （VN） prevent NB-LDPC decoder from widely applications. The decoder over GF（16） is based on the extended rain-sum （EMS） algorithm. The decoder matrix is an irregular structure as it can provide better performance than regular ones. In order to provide higher throughput and increase the parallel processing efficiency, the clock which is 8 times of the system frequency is adopted in this paper to drive the CN/VN modules. The decoder complexity can be reduced by 28% from traditional decoder when SCOMP architecture is introduced. The result of synthesis software shows that the throughput can achieve 34 Mbit/s at 10 iterations. The proposed architecture can be conveniently extended to GF such as GF（64） or GF（256）. Compared with previous works, the decoder proposed in this paper has better hardware efficiency for practical applications.
文摘In this paper, we propose to generalize the coding schemes first proposed by Kozic &al to high spectral efficient modulation schemes. We study at first Chaos Coded Modulation based on the use of small dimensional modulo-MAP encoding process and we give a solution to study the distance spectrum of such coding schemes to accurately predict their performances. However, the obtained performances are quite poor. To improve them, we use then a high dimensional modulo-MAP mapping process similar to the low-density generator-matrix codes (LDGM) introduced by Kozic &al. The main difference with their work is that we use an encoding and decoding process on GF (2m) which enables to obtain better performances while preserving a quite simple decoding algorithm when we use the Extended Min-Sum (EMS) algorithm of Declercq &Fossorier.
基金Supported by the National Natural Science Foundation of China (61205116)
文摘The complexity/performance balanced decoder for low-density parity-check （LDPC） codes is preferred in practical wireless communication systems. A low complexity LDPC decoder for the Consultative Committee for Space Data Systems （CCSDS） standard is achieved in DSP. An ap- proximate decoding algorithm, normalized rain-sum algorithm, is used in the implementation for its low amounts of computation. To reduce the performance loss caused by the approximation, the pa- rameters of the normalized min-sum algorithm are determined by calculating and finding the mini- mum value of thresholds through density evolution. The minimum value which indicates the best per- formance of the decoding algorithm is corresponding with the optimized parameters. In implementa- tion, the memory cost is saved by decomposing the parity-check matrix into submatrices to store and the computation of passing message in decoding is accelerated by using the intrinsic function of DSP. The performance of the decoder with optimized factors is simulated and compared with the ideal BP decoder. The result shows they have about the same performance.
文摘为了降低低密度奇偶校验(Low Density Parity Check,LDPC)码的译码算法复杂度,提高译码性能,结合基于残余值的动态译码NW-RBP算法和最小和算法,提出了一种基于子迭代次数的改进NW-RBP算法,将此算法称为NW-RBPF算法。该算法在进行残余值计算时利用最小和进行计算,并且根据子迭代过程中每行迭代更新的次数,由仿真得出的收敛因子计算对残余值的补偿值。仿真结果表明,该算法的译码性能相比NW-RBP算法提高了0.05 dB,收敛速度提高了1.5倍,并且其贪婪性降低,是一种适用于LDPC码,且译码性能良好、实现复杂度较低的译码算法。
基金Project (No. 20105552) supported by the Science and Technology on Avionics Integration LaboratoryNational Aeronautical Science Foundation of China
文摘This paper describes a coded cooperative multiple-input multiple-output(MIMO) scheme,where structured low-density parity-check(LDPC) codes belonging to a family of repeat-accumulate(RA) codes are employed.The outage probability of the scheme over Rayleigh fading channels is deduced.In an unknown channel state information(CSI) scenario,adaptive transversal filters based on a spatio-temporal recursive least squares(ST-RLS) algorithm are adopted in the destination to realize receive diversity gain.Also,a joint 'Min-Sum' iterative decoding is effectively carried out in the destination.Such a decoding algorithm agrees with the bilayer Tanner graph that can be used to fully characterize two distinct structured LDPC codes employed by the source and relay.Simulation results verify the effectiveness of the adopted filter in the coded cooperative MIMO scheme.Theoretical analysis and numerical simulations show that the LDPC coded cooperative MIMO scheme can well combine cooperation diversity,multi-receive diversity,and channel coding gains,and clearly outperforms coded noncooperation schemes under the same conditions.
