摘要
根据硬件实现的要求,文中研究了LPDC码的译码算法,提出了适合硬件实现的NormalizedMin-Sum译码算法的系数,并在此基础上对该算法的量化范围和量化方案的性能进行了仿真分析,仿真结果表明均匀量化比特5,6和7的选择对于误码性能影响不大,该算法大大降低了计算复杂度和硬件实现难度,具有很好的实用价值。
Based on the demand for hardware implementation, the paper presents the decoding algorithm of LDPC code and proposes a new modification factor for Normalized Min-Sum algorithm to ease the hardware implementation. This paper describes the simulations on the performances of quantization range and quantization scheme. Simulation results show that the performances of 5, 6 or 7 quantization bits are all quite close to ideal performance. This algorithm would reduce greatly the computation complexity and the difficulty in hardware implementation.
出处
《通信技术》
2008年第12期87-88,91,共3页
Communications Technology
基金
国家自然科学基金资助项目(编号:60772164)
