针对NoC(network on chip)互连测试,提出一种结合蚂蚁算法来进行互连测试的方案。方案采用NoC重用测试访问机制,在功耗约束下,运用蚂蚁算法进行寻优,获取最优矢量集,并使测试代价更小。本文以SoCIN结构电路为平台,分别对不同规模的NoC...针对NoC(network on chip)互连测试,提出一种结合蚂蚁算法来进行互连测试的方案。方案采用NoC重用测试访问机制,在功耗约束下,运用蚂蚁算法进行寻优,获取最优矢量集,并使测试代价更小。本文以SoCIN结构电路为平台,分别对不同规模的NoC进行模拟。实验结果表明,在NoC互连测试问题上,蚂蚁算法能快速收敛到最优解,测试生成时间较短。展开更多
为解决信息处理微系统中双倍速率同步动态随机存储器(Double Data Rate,DDR)复杂互连故障的检出效率和测试成本问题,通过分析DDR典型互连故障模式,将单个存储器件的自动测试设备(Auto Test Equipment,ATE)测试算法与板级系统的系统级测...为解决信息处理微系统中双倍速率同步动态随机存储器(Double Data Rate,DDR)复杂互连故障的检出效率和测试成本问题,通过分析DDR典型互连故障模式,将单个存储器件的自动测试设备(Auto Test Equipment,ATE)测试算法与板级系统的系统级测试(System Level Test,SLT)模式相结合,提出面向DDR类存储器的测试算法和实现技术途径。并基于现场可编程门阵列(Field Programmable Gate Array,FPGA)器件实现微系统内DDR互连故障的自测试,完成了典型算法的仿真模拟和实物测试验证。相较于使用ATE测试机台的存储器测试或通过用户层测试软件的测试方案,本文所采用的FPGA嵌入特定自测试算法方案可以实现典型DDR互连故障的高效覆盖,测试效率和测试成本均得到明显改善。展开更多
To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Glo...To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Global-diagnosis sequence algorithm to replace the equal weight algorithm of primary test, and the test time is shortened without changing the fault diagnostic capability. The descriptions of five modified adaptive test algorithms are presented, and the capability comparison between the modified algorithm and the original algorithm is made to prove the validity of these algorithms.展开更多
A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updat...A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updating rule and state transition rule of AA is designed.Using mutation operator,this scheme overcomes ordinary AA’s defects of slow convergence speed,easy to get stagnate,and low ability of full search.The international standard MCM benchmark circuit provided by the MCNC group was used to verify the approach.The results of simulation experiments,which compare to the results of standard ant algorithm,genetic algorithm(GA) and other deterministic interconnecting algorithms,show that the proposed scheme can achieve high fault coverage,compact test set and short CPU time,that it is a newer optimized method deserving research.展开更多
分析了GNS(Group sequence,Net sequence and Shifted net sequence)算法存在故障混淆的可能性;对于3个网络短路的情况,论述并证明了通过适当的网络分组能够避免故障混淆的发生;进而提出了降低故障混淆发生概率的网络分组原则:使易发生...分析了GNS(Group sequence,Net sequence and Shifted net sequence)算法存在故障混淆的可能性;对于3个网络短路的情况,论述并证明了通过适当的网络分组能够避免故障混淆的发生;进而提出了降低故障混淆发生概率的网络分组原则:使易发生短路故障的网络尽可能位于同一组内;在此基础上,提出了一种基于网络短路关系图的启发式分组方法。该分组方法首先建立了反映网络间相互短路概率的网络短路关系图,然后利用图论的相关知识对分组问题进行了描述,并引入了分组的最优目标函数。考虑到多项式复杂程度的非确定性(NP)完全问题的复杂性,提出了一种启发式的分组算法。结果表明:该分组方法能够在较短的时间内寻找到较优的分组结果,减小GNS算法发生故障混淆的概率,从而提高了它的测试性能。展开更多
文摘针对NoC(network on chip)互连测试,提出一种结合蚂蚁算法来进行互连测试的方案。方案采用NoC重用测试访问机制,在功耗约束下,运用蚂蚁算法进行寻优,获取最优矢量集,并使测试代价更小。本文以SoCIN结构电路为平台,分别对不同规模的NoC进行模拟。实验结果表明,在NoC互连测试问题上,蚂蚁算法能快速收敛到最优解,测试生成时间较短。
文摘为解决信息处理微系统中双倍速率同步动态随机存储器(Double Data Rate,DDR)复杂互连故障的检出效率和测试成本问题,通过分析DDR典型互连故障模式,将单个存储器件的自动测试设备(Auto Test Equipment,ATE)测试算法与板级系统的系统级测试(System Level Test,SLT)模式相结合,提出面向DDR类存储器的测试算法和实现技术途径。并基于现场可编程门阵列(Field Programmable Gate Array,FPGA)器件实现微系统内DDR互连故障的自测试,完成了典型算法的仿真模拟和实物测试验证。相较于使用ATE测试机台的存储器测试或通过用户层测试软件的测试方案,本文所采用的FPGA嵌入特定自测试算法方案可以实现典型DDR互连故障的高效覆盖,测试效率和测试成本均得到明显改善。
文摘To study the diagnostic problem of Wire-OR （W-O） interconnect fault of PCB （Printed Circuit Board）, five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Global-diagnosis sequence algorithm to replace the equal weight algorithm of primary test, and the test time is shortened without changing the fault diagnostic capability. The descriptions of five modified adaptive test algorithms are presented, and the capability comparison between the modified algorithm and the original algorithm is made to prove the validity of these algorithms.
文摘A novel multi-chip module(MCM) interconnect test generation scheme based on ant algorithm(AA) with mutation operator was presented.By combing the characteristics of MCM interconnect test generation,the pheromone updating rule and state transition rule of AA is designed.Using mutation operator,this scheme overcomes ordinary AA’s defects of slow convergence speed,easy to get stagnate,and low ability of full search.The international standard MCM benchmark circuit provided by the MCNC group was used to verify the approach.The results of simulation experiments,which compare to the results of standard ant algorithm,genetic algorithm(GA) and other deterministic interconnecting algorithms,show that the proposed scheme can achieve high fault coverage,compact test set and short CPU time,that it is a newer optimized method deserving research.
文摘分析了GNS(Group sequence,Net sequence and Shifted net sequence)算法存在故障混淆的可能性;对于3个网络短路的情况,论述并证明了通过适当的网络分组能够避免故障混淆的发生;进而提出了降低故障混淆发生概率的网络分组原则:使易发生短路故障的网络尽可能位于同一组内;在此基础上,提出了一种基于网络短路关系图的启发式分组方法。该分组方法首先建立了反映网络间相互短路概率的网络短路关系图,然后利用图论的相关知识对分组问题进行了描述,并引入了分组的最优目标函数。考虑到多项式复杂程度的非确定性(NP)完全问题的复杂性,提出了一种启发式的分组算法。结果表明:该分组方法能够在较短的时间内寻找到较优的分组结果,减小GNS算法发生故障混淆的概率,从而提高了它的测试性能。
