This paper proposes a method of using multi controllers to control supermaneuverable aircraft. A nonlinear dynamic inversion controller is used for supermaneuver. A gain scheduled controller is used for routine man...This paper proposes a method of using multi controllers to control supermaneuverable aircraft. A nonlinear dynamic inversion controller is used for supermaneuver. A gain scheduled controller is used for routine maneuver. A switch algorithm is designed to switch the controllers. The flight envelopes of the controllers are different but have a common area in which the controllers are switched from one to the other. In the common area, some special boundaries are selected to decide switch conditions. The controllers all use vector thrust for lower velocity maneuver control. Unlike the variation structure theory to use a single boundary, this paper uses two boundaries for switching between the two controllers. One boundary is used for switching from dynamic inversion to gain scheduling, while the other is used for switching from gain scheduling to dynamic inversion. This can effectively avoid the system vibration caused by switching repeatedly at a single boundary. The method is very easy for engineering. It can reduce the risk of design of the supermaneuverable aircraft.展开更多
A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor...A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.展开更多
基于线型腔结构实现中心波长约1 945 nm、功率150 m W的连续激光输出,采用3级主振荡功率放大(master oscillator power amplifier,MOPA)结构,实现123 W的掺铥激光输出,斜率效率为59.1%.搭建基于调制半导体激光器,输出波长为1 550 nm的...基于线型腔结构实现中心波长约1 945 nm、功率150 m W的连续激光输出,采用3级主振荡功率放大(master oscillator power amplifier,MOPA)结构,实现123 W的掺铥激光输出,斜率效率为59.1%.搭建基于调制半导体激光器,输出波长为1 550 nm的铒镱共掺光纤放大器,实现平均功率1.2 W、脉宽50 ns、重复频率200 k Hz的脉冲激光输出.将该铒镱共掺光纤放大器作为泵浦源,采用线型腔结构抽运掺铥光纤,实现中心波长约为1 945 nm的增益调制脉冲激光输出,重复频率为100 k Hz,脉宽约为800ns.采用3级MOPA结构对此增益调制掺铥脉冲光纤激光器进行功率放大,实现平均功率115 W、单脉冲能量1.15 m J的激光输出,且放大过程中无非线性效应产生.展开更多
This paper presents a two-channel 12-bit current-steering digital-to-analog converter（DAC） for I and Q signal paths in a wireless transmitter.The proposed DAC has a full-scale output current with an adjusting range ...This paper presents a two-channel 12-bit current-steering digital-to-analog converter（DAC） for I and Q signal paths in a wireless transmitter.The proposed DAC has a full-scale output current with an adjusting range of 2 to 10 mA.A gain matching circuit is proposed to reduce gain mismatch between the I and Q channels.The tuning range is±24%of full scale and the minimum resolution is 1/16 LSB.To further improve its dynamic performance, the switch driver and current cell are optimized to minimize glitch energy.The chip has been processed in a standard 0.13μm CMOS technology.Gain mismatch between a 1-channel DAC and a Q-channel DAC is measured to be approximately 0.13%.At 120-MSPS sample rate for 1 MHz sinusoidal signal,the spurious free dynamic range （SFDR） is 75 dB.The total power dissipation is 62 mW and has an active area of 1.08 mm^2.展开更多
A high performance sample-and-hold(S/H) circuit used in a pipelined analog-to-digital converter(ADC) is presented in this paper. Fully-differential capacitor flip-around architecture was used in this S/H circuit.A gai...A high performance sample-and-hold(S/H) circuit used in a pipelined analog-to-digital converter(ADC) is presented in this paper. Fully-differential capacitor flip-around architecture was used in this S/H circuit.A gain-boosted folded cascode operational transconductance amplifier(OTA) with a DC gain of 90 dB and a GBW of 738 MHz was designed. A low supply voltage bootstrapped switch was used to improve the linearity of the S/H circuit. With these techniques, the designed S/H circuit can reach 94 dB SFDR for a 48.9 MHz input frequency with 100 MS/s sampling rate. Measurement results of a 14-bit 100-MS/s pipeline ADC with designed S/H circuit are presented.展开更多
文摘This paper proposes a method of using multi controllers to control supermaneuverable aircraft. A nonlinear dynamic inversion controller is used for supermaneuver. A gain scheduled controller is used for routine maneuver. A switch algorithm is designed to switch the controllers. The flight envelopes of the controllers are different but have a common area in which the controllers are switched from one to the other. In the common area, some special boundaries are selected to decide switch conditions. The controllers all use vector thrust for lower velocity maneuver control. Unlike the variation structure theory to use a single boundary, this paper uses two boundaries for switching between the two controllers. One boundary is used for switching from dynamic inversion to gain scheduling, while the other is used for switching from gain scheduling to dynamic inversion. This can effectively avoid the system vibration caused by switching repeatedly at a single boundary. The method is very easy for engineering. It can reduce the risk of design of the supermaneuverable aircraft.
文摘A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.
文摘基于线型腔结构实现中心波长约1 945 nm、功率150 m W的连续激光输出,采用3级主振荡功率放大(master oscillator power amplifier,MOPA)结构,实现123 W的掺铥激光输出,斜率效率为59.1%.搭建基于调制半导体激光器,输出波长为1 550 nm的铒镱共掺光纤放大器,实现平均功率1.2 W、脉宽50 ns、重复频率200 k Hz的脉冲激光输出.将该铒镱共掺光纤放大器作为泵浦源,采用线型腔结构抽运掺铥光纤,实现中心波长约为1 945 nm的增益调制脉冲激光输出,重复频率为100 k Hz,脉宽约为800ns.采用3级MOPA结构对此增益调制掺铥脉冲光纤激光器进行功率放大,实现平均功率115 W、单脉冲能量1.15 m J的激光输出,且放大过程中无非线性效应产生.
基金supported by the National Science and Technology Major Projects of China(No.2010ZX03002-001-02)the Fundamental Research Funds for the Central Universities(No.K50511250006)
文摘This paper presents a two-channel 12-bit current-steering digital-to-analog converter（DAC） for I and Q signal paths in a wireless transmitter.The proposed DAC has a full-scale output current with an adjusting range of 2 to 10 mA.A gain matching circuit is proposed to reduce gain mismatch between the I and Q channels.The tuning range is±24%of full scale and the minimum resolution is 1/16 LSB.To further improve its dynamic performance, the switch driver and current cell are optimized to minimize glitch energy.The chip has been processed in a standard 0.13μm CMOS technology.Gain mismatch between a 1-channel DAC and a Q-channel DAC is measured to be approximately 0.13%.At 120-MSPS sample rate for 1 MHz sinusoidal signal,the spurious free dynamic range （SFDR） is 75 dB.The total power dissipation is 62 mW and has an active area of 1.08 mm^2.
文摘A high performance sample-and-hold(S/H) circuit used in a pipelined analog-to-digital converter(ADC) is presented in this paper. Fully-differential capacitor flip-around architecture was used in this S/H circuit.A gain-boosted folded cascode operational transconductance amplifier(OTA) with a DC gain of 90 dB and a GBW of 738 MHz was designed. A low supply voltage bootstrapped switch was used to improve the linearity of the S/H circuit. With these techniques, the designed S/H circuit can reach 94 dB SFDR for a 48.9 MHz input frequency with 100 MS/s sampling rate. Measurement results of a 14-bit 100-MS/s pipeline ADC with designed S/H circuit are presented.
