A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and lead...A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_（sp） is reduced from 16.5 to 13.8 mΩ·cm^2 in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV^2/R_（on）.It reduces R_（sp） by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.展开更多
A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an e...A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. An economical manufacturing process, requiring only 10 masking steps, yields a broad range of MOS and bipolar components integrated on a common substrate, including 700 V nLDMOS, 200 V nLDMOS, 80 V nLDMOS, 60 V nLDMOS, 40 V nLDMOS, 700 V nJFET, and low voltage devices. A robust double RESURF nLDMOS with a breakdown voltage of 800 V and specific on-resistance of 206.2 mf2.cm2 is successfully optimized and realized. The results of this technology are low fabrication cost, simple process and small chip area for PIC products.展开更多
RESURF LDM O S很难兼顾击穿电压和导通电阻对结构的要求。文中采用了D oub le RESURF(双重降低表面电场)新结构,使漂移区更易耗尽。从理论和模拟上验证了D oub le RESURF在漂移区浓度不变时对击穿电压的提高作用以及在保持击穿电压不...RESURF LDM O S很难兼顾击穿电压和导通电阻对结构的要求。文中采用了D oub le RESURF(双重降低表面电场)新结构,使漂移区更易耗尽。从理论和模拟上验证了D oub le RESURF在漂移区浓度不变时对击穿电压的提高作用以及在保持击穿电压不变的情况下减小导通电阻的效果。同时,在LDM O S结构中加入D oub leRESURF结构也降低了工艺上对精度的要求。为新结构和新工艺的开发研制作前期设计和评估。展开更多
建立了Double-RESURF结构高压LDMOS器件的MOS+VCR(Voltage Control Re-sistance)电路模型。通过分析Double-RESURF LDMOS器件的结构与输入输出特性,得到漂移区电阻的解析式;借助泰勒展式,得到VCR的高阶压控模型,从而建立LDMOS器件的SPIC...建立了Double-RESURF结构高压LDMOS器件的MOS+VCR(Voltage Control Re-sistance)电路模型。通过分析Double-RESURF LDMOS器件的结构与输入输出特性,得到漂移区电阻的解析式;借助泰勒展式,得到VCR的高阶压控模型,从而建立LDMOS器件的SPICE模型。该模型的解析解和数值解符合良好,而且体现出高压LDMOS的准饱和特性。模型的建立可以很好地指导LDMOS器件的工程应用。展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.60806025,60976060)
文摘A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_（sp） is reduced from 16.5 to 13.8 mΩ·cm^2 in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV^2/R_（on）.It reduces R_（sp） by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.
基金Project supported by the Young Scientists Fund of the National Natural Science Foundation of China(No.60906038)
文摘A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. An economical manufacturing process, requiring only 10 masking steps, yields a broad range of MOS and bipolar components integrated on a common substrate, including 700 V nLDMOS, 200 V nLDMOS, 80 V nLDMOS, 60 V nLDMOS, 40 V nLDMOS, 700 V nJFET, and low voltage devices. A robust double RESURF nLDMOS with a breakdown voltage of 800 V and specific on-resistance of 206.2 mf2.cm2 is successfully optimized and realized. The results of this technology are low fabrication cost, simple process and small chip area for PIC products.
文摘RESURF LDM O S很难兼顾击穿电压和导通电阻对结构的要求。文中采用了D oub le RESURF(双重降低表面电场)新结构,使漂移区更易耗尽。从理论和模拟上验证了D oub le RESURF在漂移区浓度不变时对击穿电压的提高作用以及在保持击穿电压不变的情况下减小导通电阻的效果。同时,在LDM O S结构中加入D oub leRESURF结构也降低了工艺上对精度的要求。为新结构和新工艺的开发研制作前期设计和评估。
文摘建立了Double-RESURF结构高压LDMOS器件的MOS+VCR(Voltage Control Re-sistance)电路模型。通过分析Double-RESURF LDMOS器件的结构与输入输出特性,得到漂移区电阻的解析式;借助泰勒展式,得到VCR的高阶压控模型,从而建立LDMOS器件的SPICE模型。该模型的解析解和数值解符合良好,而且体现出高压LDMOS的准饱和特性。模型的建立可以很好地指导LDMOS器件的工程应用。
