期刊文献+

LDMOS漂移区结构优化的模拟 被引量:1

Simulation of LDMOS Drift Region Structure Optimization
下载PDF
导出
摘要 RESURF LDM O S很难兼顾击穿电压和导通电阻对结构的要求。文中采用了D oub le RESURF(双重降低表面电场)新结构,使漂移区更易耗尽。从理论和模拟上验证了D oub le RESURF在漂移区浓度不变时对击穿电压的提高作用以及在保持击穿电压不变的情况下减小导通电阻的效果。同时,在LDM O S结构中加入D oub leRESURF结构也降低了工艺上对精度的要求。为新结构和新工艺的开发研制作前期设计和评估。 A conventional RESURF LDMOS could not be possessed of a high off-state breakdown voltage while achieving a low on-state resistance. To make drift region depletion much easier,a Double RESURF(Double REduce SURFace electronic field) structure is studied in this paper. The mechanism of raising breakdown voltage in the same concentration of drift region as RESURF LDMOS,and reducing the on-state resistance while preventing the breakdown voltage from dropping,is both analyzed theoretically and verified by simulation. A simplified process of the structure is proposed in brief. Also the evaluation for the new process is carried out.
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2006年第1期6-10,共5页 Research & Progress of SSE
关键词 横向双扩散金属氧化物晶体管 双重降低表面电场 P型表面注入层 导通电阻 击穿电压 LDMOS Double RESURF P-top on-state resistance breakdown voltage
  • 相关文献

参考文献7

  • 1Appels J A,H M J Vaes.High voltage thin layer device (RESURF devices)[A].IEDM Tech Digest[C].1979:238-241 被引量:1
  • 2Disney D R,Paul A K,Darwish M,et al.A new 800 V lateral MOSFET with dual conduction paths [A ].Proceedings of 2001 International Symposium on Power Semiconductor Devices & ICs[C].Osaka,2001:399-402 被引量:1
  • 3Baliga B J,Ghandhi S K.Analytical solutions for the breakdown voltage of abrupt cylindrical and spherical junctions[J].Solid State Electronics,1976;19:739-744 被引量:1
  • 4黄飞鸿,郑国祥,吴瑞.双层多晶硅FLOTOX EEPROM特性的模拟和验证[J].Journal of Semiconductors,2003,24(6):637-642. 被引量:2
  • 5ATLAS Two-Dimensional Device Simulation Program User's Manual [M ].Silvaco International,1998:165-168. 被引量:1
  • 6Stanley Wolf.Silicon Processing for the VLSI Era[M].Sunset Beach,Califormia:Lattice Press,1990:296-298 被引量:1
  • 7Choi Y S,Jeon C K,Kim J J.800V BCD 1chip Process for Smart Power IC [ M ].New Technology Development Team,Fairchild Semiconductor,2000:3 被引量:1

二级参考文献9

  • 1Sucin P I,Cox B P,Rinerson D D,et al.Cell model for EEPROM floating-gate memories.In:IDEM Tech Dig.San Fracisco,1982:737 被引量:1
  • 2Kuo C,Yeargain J R,Downney W J,et al.IEEE J Solid-State Circuits,1982,5c-17:821 被引量:1
  • 3Lenzlinger M,Snow E H.Fowler-Nordeim tunneling in thermally grown SiO2.J Appl Phys,1969,40:278 被引量:1
  • 4Brown W D,Brewer J E.Nonvolatile semiconductor memory technology.The Institute of Electrical and Electronics Engineers,Inc,New York 被引量:1
  • 5Bhattacharyya A.Modelling of write/erase and charge retention characteristics of floating gate EEPROM devices.Solid-State Electron,1984,10:899 被引量:1
  • 6Cricchi J R,Blaha F C,Fitzpatrick M D.The drain-source protected MNOS memory device and memory endurance.IEEE IEDM Tech Dig,1973:126 被引量:1
  • 7Landers G.5-V-only EEPROM mimics static RAM timing.Electronics,1980:127 被引量:1
  • 8Harari E,Schmitz L,Troutman B,et al.A 256bit non-volatile static RAM.IEEE ISSCC Dig Tech,1978:108 被引量:1
  • 9洪志良,韩兴成,李兴仁,付志军,黄震,束克留.电可擦除存储器单元的模型[J].Journal of Semiconductors,1999,20(9):786-791. 被引量:2

共引文献1

同被引文献5

  • 1王书凯,程东方,徐志平,沈文星.适用于智能功率IC的700v Double-Resurf Ldmos研究[J].微计算机信息,2007,23(23):270-271. 被引量:5
  • 2Jacob B R.CMOS电路设计、布局与仿真[M].刘艳艳,译.北京:人民邮电出版社,2008:340-358. 被引量:2
  • 3ANNGHEL C, HEFYENE N, IONESCU A M, et al. Physical modeling strategy for(quasi-) saturation effects in lateral DMOS transistor based on the concept of intrinsic drain voltage [ C]// Proc of USA international Semiconductor Conference CAS. USA, 2001,2:417-420. 被引量:1
  • 4刘恩科,张华曹,柴常春.半导体器件物理[M].北京:电子工业出版社,2006.248-250. 被引量:1
  • 5UTMOST III Extraction Manual. Volume 1 MOSEFT and TFT Modeling Routines [ K ]. California, USA: Simucad Design Automation, 2006: 533 - 546. 被引量:1

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部