大规模相控阵是解决毫米波无线传输距离受限的核心关键技术.传统的毫米波相控阵通常基于化合物半导体芯片加以实现,该类芯片成本高昂且难以实现系统单片集成,极大地限制了传统相控阵的应用范围.本文报道了基于CMOS成熟工艺的毫米波芯片...大规模相控阵是解决毫米波无线传输距离受限的核心关键技术.传统的毫米波相控阵通常基于化合物半导体芯片加以实现,该类芯片成本高昂且难以实现系统单片集成,极大地限制了传统相控阵的应用范围.本文报道了基于CMOS成熟工艺的毫米波芯片设计及收发通道数为4096(4096发射/4096接收)的超大规模集成相控阵实现技术.CMOS体硅工艺具有集成度高、成本低廉等优势,但面临有源器件高频性能差、无源器件及互连线高频损耗大、高低温性能差异大等一系列技术瓶颈.通过引入电流复用跨导增强型低噪声放大器、基于新型版图结构的高效率功率放大器、矢量调制型数控无源移相器、基于电容补偿的超宽带衰减器、紧凑型功分器,以及高低温自适应偏置电路等技术,可以较好地解决CMOS体硅工艺所面临的上述瓶颈问题.基于65 nm CMOS体硅工艺,所实现的Ka频段CMOS相控阵芯片噪声系数为3.0 d B,发射通道效率为15%,无需校准即可实现精确幅相控制,相关测试结果表明所研制的低成本相控阵芯片具有集成度高、幅相控制精确等优势,噪声系数等关键技术指标接近砷化镓工艺.以此为基础,本文给出了基于多层混压PCB工艺的1024发射/1024接收超大规模"集成相控阵"设计技术,并将其扩展至4096发射/4096接收相控阵规模,最后给出了低成本、高集成宽带卫星移动通信终端在车载和船载条件下的示范应用结果.展开更多
The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for th...The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.37 mm2.展开更多
A reconfigurable multi-mode direct-conversion transmitter （TX） with integrated frequency synthe sizer （FS） is presented. The TX as well as the FS is designed with a flexible architecture and frequency plan, which ...A reconfigurable multi-mode direct-conversion transmitter （TX） with integrated frequency synthe sizer （FS） is presented. The TX as well as the FS is designed with a flexible architecture and frequency plan, which helps to support all the 433/868/915 MHz ISM band signals, with the reconfigurable bandwidth from 250 kHz to 2 MHz. In order to save power and chip area, only one 1.8 GHz VCO is adopted to cover the whole frequency range. All the operation modes can be regulated in real time by configuring the integrated register-bank through an SPI interface. Implemented in 180 nm CMOS, the FS achieves a frequency coverage of 320-460 MHz and 620- 920 MHz. The lowest phase noise can be -107 dBc/Hz at a 100 kHz offset and-126 dBc/Hz at a 1 MHz offset. The transmitter features a 10.2 dBm peak output power with a ＋9.5 dBm 1-dB-compression point and 250 kHz/500 kHz/1 MHz/2 MHz reconfigurable signal bandwidth.展开更多
A highly linear,high output power,0.13μm CMOS direct conversion transmitter for wideband code division multiple access（WCDMA） is described.The transmitter delivers 6.8 dBm output power with 38 mA current consumptio...A highly linear,high output power,0.13μm CMOS direct conversion transmitter for wideband code division multiple access（WCDMA） is described.The transmitter delivers 6.8 dBm output power with 38 mA current consumption.With careful design on the resistor bank in the IQ-modulator,the gain step accuracy is within 0.1 dB,hence the image rejection ratio can be kept below—47 dBc for the entire output range.The adjacent channel leakage ratio and the LO leakage at 6.8 dBm output power are -44 dBc @ 5 MHz and -37 dBc,respectively,and the corresponding EVM is 3.6%.The overall gain can be programmed in 6 dB steps in a 66-dB range.展开更多
This paper presents a fully integrated dual-mode 6 to 9 GHz transmitter for both WiMedia and China MB-OFDM UWB applications. The proposed transmitter consists of a dual-mode I/Q LPF, an up-conversion mixer, a two-stag...This paper presents a fully integrated dual-mode 6 to 9 GHz transmitter for both WiMedia and China MB-OFDM UWB applications. The proposed transmitter consists of a dual-mode I/Q LPF, an up-conversion mixer, a two-stage power driver amplifier and a broadband high-speed frequency divider with LO buffers for I/Q LO carrier generation. The measurement results show that the gain ripple of the transmitter is within ±1.5/±2.8 dB from 6 to 8.7/9 GHz. The output IP3 is about ＋13.2 dBm, the output 1 dBCP is around ＋2.8 dBm, and the LO leakage/sideband rejection ratio is about-35/-38 dBc. The ESD protected chip is fabricated with a TSMC 0.13 μm RFCMOS process with a die size of 1.6 × 1.3 mm^2 and the core circuit consumes only 46 mA under a 1.2 V supply.展开更多
This paper presents a first monolithic RF transceiver for DC-OFDM UWB applications.The proposed direct-conversion transceiver integrates all the building blocks including two receiver（Rx） cores,two transmitter （Tx...This paper presents a first monolithic RF transceiver for DC-OFDM UWB applications.The proposed direct-conversion transceiver integrates all the building blocks including two receiver（Rx） cores,two transmitter （Tx） cores and a dual-carrier frequency synthesizer（DC-FS） as well as a 3-wire serial peripheral interface（SPI） to set the operating status of the transceiver.The ESD-protected chip is fabricated by a TSMC 0.13-μm RF CMOS process with a die size of 4.5 x 3.6 mm2.The measurement results show that the wideband Rx achieves an NF of 5-6.2 dB,a max gain of 76-84 dB with 64-dB variable gain,an in-/out-of-band IIP3 of-6/＋4 dBm and an input loss S11 of〈-10 in all bands.The Tx achieves an LOLRR/IMGRR of-34/-33 dBc,a typical OIP3 of＋6 dBm and a maximum output power of -5 dBm.The DC-FS outputs two separate carriers simultaneously with an inter-band hopping time of〈1.2 ns.The full chip consumes a maximum current of 420 mA under a 1.2-V supply.展开更多
Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modu...Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modulator, and a control logic unit. The direct-conversion architecture minimizes the required on-and-off-chip components and provides a low-cost and efficient solution. A novel structure is proposed to provide the modulation depth of 100% and 18% ,respectively. The PA presents an output ldB power of 17.6dBm while maintaining a maximum PAE of 35.4%.展开更多
With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper first...With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper firstly explains the benefits and design implications of the hybrid beamforming structure in terms of the mmWave spectrum characteristics,energy efficiency,data rate,communication capacity,coverage and implementation technology choices.Then after reviewing the techniques to improve the power amplifier(PA)output power and efficiency,the design considerations and test results of 60 GHz and 90 GHz mmWave PAs in bulk complementary metal oxide semiconductor(CMOS)process are shown.展开更多
This paper presents the experimental results of a low-power RF transmitter for 2.4-GHz-band IEEE 802.15.4 standard in 0.18-μm CMOS technology. In order to make an adaptive RF transmitter, several factors must be cons...This paper presents the experimental results of a low-power RF transmitter for 2.4-GHz-band IEEE 802.15.4 standard in 0.18-μm CMOS technology. In order to make an adaptive RF transmitter, several factors must be considered. The most important factors are performances, power consumption, output power, noise factor, and cost. The RF transmitter comprises a quadrature passive mixer, and a power amplifier. The proposed RF transmitter consumes only 10.8-mW under a supply voltage of 1.8-V.展开更多
文摘大规模相控阵是解决毫米波无线传输距离受限的核心关键技术.传统的毫米波相控阵通常基于化合物半导体芯片加以实现,该类芯片成本高昂且难以实现系统单片集成,极大地限制了传统相控阵的应用范围.本文报道了基于CMOS成熟工艺的毫米波芯片设计及收发通道数为4096(4096发射/4096接收)的超大规模集成相控阵实现技术.CMOS体硅工艺具有集成度高、成本低廉等优势,但面临有源器件高频性能差、无源器件及互连线高频损耗大、高低温性能差异大等一系列技术瓶颈.通过引入电流复用跨导增强型低噪声放大器、基于新型版图结构的高效率功率放大器、矢量调制型数控无源移相器、基于电容补偿的超宽带衰减器、紧凑型功分器,以及高低温自适应偏置电路等技术,可以较好地解决CMOS体硅工艺所面临的上述瓶颈问题.基于65 nm CMOS体硅工艺,所实现的Ka频段CMOS相控阵芯片噪声系数为3.0 d B,发射通道效率为15%,无需校准即可实现精确幅相控制,相关测试结果表明所研制的低成本相控阵芯片具有集成度高、幅相控制精确等优势,噪声系数等关键技术指标接近砷化镓工艺.以此为基础,本文给出了基于多层混压PCB工艺的1024发射/1024接收超大规模"集成相控阵"设计技术,并将其扩展至4096发射/4096接收相控阵规模,最后给出了低成本、高集成宽带卫星移动通信终端在车载和船载条件下的示范应用结果.
文摘The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.37 mm2.
文摘A reconfigurable multi-mode direct-conversion transmitter （TX） with integrated frequency synthe sizer （FS） is presented. The TX as well as the FS is designed with a flexible architecture and frequency plan, which helps to support all the 433/868/915 MHz ISM band signals, with the reconfigurable bandwidth from 250 kHz to 2 MHz. In order to save power and chip area, only one 1.8 GHz VCO is adopted to cover the whole frequency range. All the operation modes can be regulated in real time by configuring the integrated register-bank through an SPI interface. Implemented in 180 nm CMOS, the FS achieves a frequency coverage of 320-460 MHz and 620- 920 MHz. The lowest phase noise can be -107 dBc/Hz at a 100 kHz offset and-126 dBc/Hz at a 1 MHz offset. The transmitter features a 10.2 dBm peak output power with a ＋9.5 dBm 1-dB-compression point and 250 kHz/500 kHz/1 MHz/2 MHz reconfigurable signal bandwidth.
基金Project supported by the National High Technology Research and Development of China(No.2009AA011605)
文摘A highly linear,high output power,0.13μm CMOS direct conversion transmitter for wideband code division multiple access（WCDMA） is described.The transmitter delivers 6.8 dBm output power with 38 mA current consumption.With careful design on the resistor bank in the IQ-modulator,the gain step accuracy is within 0.1 dB,hence the image rejection ratio can be kept below—47 dBc for the entire output range.The adjacent channel leakage ratio and the LO leakage at 6.8 dBm output power are -44 dBc @ 5 MHz and -37 dBc,respectively,and the corresponding EVM is 3.6%.The overall gain can be programmed in 6 dB steps in a 66-dB range.
基金Project supported by the National Science and Technology Major Projects of China(Nos.2009ZX03006-007-01,2009ZX03007-001, 2009ZX03006-009)the National High Technology R&D Program of China(No.2009AA01Z261).
文摘This paper presents a fully integrated dual-mode 6 to 9 GHz transmitter for both WiMedia and China MB-OFDM UWB applications. The proposed transmitter consists of a dual-mode I/Q LPF, an up-conversion mixer, a two-stage power driver amplifier and a broadband high-speed frequency divider with LO buffers for I/Q LO carrier generation. The measurement results show that the gain ripple of the transmitter is within ±1.5/±2.8 dB from 6 to 8.7/9 GHz. The output IP3 is about ＋13.2 dBm, the output 1 dBCP is around ＋2.8 dBm, and the LO leakage/sideband rejection ratio is about-35/-38 dBc. The ESD protected chip is fabricated with a TSMC 0.13 μm RFCMOS process with a die size of 1.6 × 1.3 mm^2 and the core circuit consumes only 46 mA under a 1.2 V supply.
基金supported by the National Science & Technology Major Projects of China(No.2009ZX03006-007-01)the National High Technology R&D Program of China(No.2009AA01 Z261)
文摘This paper presents a first monolithic RF transceiver for DC-OFDM UWB applications.The proposed direct-conversion transceiver integrates all the building blocks including two receiver（Rx） cores,two transmitter （Tx） cores and a dual-carrier frequency synthesizer（DC-FS） as well as a 3-wire serial peripheral interface（SPI） to set the operating status of the transceiver.The ESD-protected chip is fabricated by a TSMC 0.13-μm RF CMOS process with a die size of 4.5 x 3.6 mm2.The measurement results show that the wideband Rx achieves an NF of 5-6.2 dB,a max gain of 76-84 dB with 64-dB variable gain,an in-/out-of-band IIP3 of-6/＋4 dBm and an input loss S11 of〈-10 in all bands.The Tx achieves an LOLRR/IMGRR of-34/-33 dBc,a typical OIP3 of＋6 dBm and a maximum output power of -5 dBm.The DC-FS outputs two separate carriers simultaneously with an inter-band hopping time of〈1.2 ns.The full chip consumes a maximum current of 420 mA under a 1.2-V supply.
文摘Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modulator, and a control logic unit. The direct-conversion architecture minimizes the required on-and-off-chip components and provides a low-cost and efficient solution. A novel structure is proposed to provide the modulation depth of 100% and 18% ,respectively. The PA presents an output ldB power of 17.6dBm while maintaining a maximum PAE of 35.4%.
基金supported by the National Natural Science Foundations of China (Nos. 61306030, 61674037)the National Key R&D Program of China (Nos.2016YFC0800400, 2018YFE0205900)the National Science and Technology Major Project (No. 2018ZX03001008)
文摘With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper firstly explains the benefits and design implications of the hybrid beamforming structure in terms of the mmWave spectrum characteristics,energy efficiency,data rate,communication capacity,coverage and implementation technology choices.Then after reviewing the techniques to improve the power amplifier(PA)output power and efficiency,the design considerations and test results of 60 GHz and 90 GHz mmWave PAs in bulk complementary metal oxide semiconductor(CMOS)process are shown.
文摘This paper presents the experimental results of a low-power RF transmitter for 2.4-GHz-band IEEE 802.15.4 standard in 0.18-μm CMOS technology. In order to make an adaptive RF transmitter, several factors must be considered. The most important factors are performances, power consumption, output power, noise factor, and cost. The RF transmitter comprises a quadrature passive mixer, and a power amplifier. The proposed RF transmitter consumes only 10.8-mW under a supply voltage of 1.8-V.
