This paper shows the design of a second-order multi-bit△Σmodulator with hybrid structure for ADSL applications.A modified two phase non-overlapping clock generator is designed to let PH2 borrow 12%of the time from P...This paper shows the design of a second-order multi-bit△Σmodulator with hybrid structure for ADSL applications.A modified two phase non-overlapping clock generator is designed to let PH2 borrow 12%of the time from PH1,which relaxes the speed of OTAs,comparators and the DEM block.The clock feed through problem of the passive adder is solved by revising the timing of the comparators and the adder.The chip is designed and fabricated in UMC 0.18μm CMOS technology.Measurement results show that with an oversampling ratio of 32 and a clock rate of 80 MHz,the modulator can achieve 79 dB dynamic range,71.3 dB SNDR,11 mW power consumption from a 1.8 V power supply.The FOM is 1.47 pJ/step.展开更多
A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a ...A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10^-6, the testing results show that the phase noises are –120.6 dBc/Hz at 1 MHz and –95.0 dBc/Hz at 100 k Hz. The chip is2.1 mm^2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.展开更多
This paper introduces a low-noise low-costΣA modulator for digital audio analog-to-digital conversion. By adopting a low-noise large-output swing operation amplifier,not only is the flicker noise greatly inhibited,bu...This paper introduces a low-noise low-costΣA modulator for digital audio analog-to-digital conversion. By adopting a low-noise large-output swing operation amplifier,not only is the flicker noise greatly inhibited,but also the power consumption is reduced.Also the area cost is relatively small.The modulator was implemented in a SMIC standard 65-nm CMOS process.Measurement results show it can achieve 96 dB peak signal-to-noise plus distortion ratio（SNDR） and 105 dB dynamic range（DR） over the 22.05-kHz audio band and occupies 0.16 mm^2. The power consumption of the proposed modulator is 4.9 mW from a 2.5 V power supply,which is suitable for high-performance,low-cost audio codec applications.展开更多
基金supported by the National High Technology Research and Development Program of China(No.2008AA010700)
文摘This paper shows the design of a second-order multi-bit△Σmodulator with hybrid structure for ADSL applications.A modified two phase non-overlapping clock generator is designed to let PH2 borrow 12%of the time from PH1,which relaxes the speed of OTAs,comparators and the DEM block.The clock feed through problem of the passive adder is solved by revising the timing of the comparators and the adder.The chip is designed and fabricated in UMC 0.18μm CMOS technology.Measurement results show that with an oversampling ratio of 32 and a clock rate of 80 MHz,the modulator can achieve 79 dB dynamic range,71.3 dB SNDR,11 mW power consumption from a 1.8 V power supply.The FOM is 1.47 pJ/step.
文摘A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10^-6, the testing results show that the phase noises are –120.6 dBc/Hz at 1 MHz and –95.0 dBc/Hz at 100 k Hz. The chip is2.1 mm^2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.
基金supported by the PhD Programs Foundation of Ministry of Education of China(No.20100101110063)the Incubation Programs of Innovation & Carve out of Zhejiang Province,China
文摘This paper introduces a low-noise low-costΣA modulator for digital audio analog-to-digital conversion. By adopting a low-noise large-output swing operation amplifier,not only is the flicker noise greatly inhibited,but also the power consumption is reduced.Also the area cost is relatively small.The modulator was implemented in a SMIC standard 65-nm CMOS process.Measurement results show it can achieve 96 dB peak signal-to-noise plus distortion ratio（SNDR） and 105 dB dynamic range（DR） over the 22.05-kHz audio band and occupies 0.16 mm^2. The power consumption of the proposed modulator is 4.9 mW from a 2.5 V power supply,which is suitable for high-performance,low-cost audio codec applications.
