设计了一种基于1 bit Sigma-Delta环路调制技术的高精度数字磁通门磁强计,建立了数字磁强计信号处理仿真模型,并利用Matlab的Simulink仿真工具开展了数字磁通门磁强计模型的仿真分析,对数字磁强计系统的噪声、线性度、响应速度和频率响...设计了一种基于1 bit Sigma-Delta环路调制技术的高精度数字磁通门磁强计,建立了数字磁强计信号处理仿真模型,并利用Matlab的Simulink仿真工具开展了数字磁通门磁强计模型的仿真分析,对数字磁强计系统的噪声、线性度、响应速度和频率响应进行了仿真计算。利用本文1 bit Sigma-Delta环路调制技术的数字磁强计在量程超过±10^(5 )nT的情况下,系统在1 Hz处的噪声仅为4.66 pT·Hz^(-1/2),最大线性偏差为0.16 nT,动态响应速度达到2×10^(6) nT·s^(–1),频率响应带宽超过10 Hz。仿真结果表明,基于1 bit Sigma-Delta环路调制技术的数字磁通门磁强计可以有效降低对A/D转换器精度的要求,在保证性能的前提下大幅度降低了电路复杂程度,提高了系统的可靠性,在深空探测、空间磁场测量等领域具有广泛的应用前景。展开更多
An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its su...An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.展开更多
Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode（DCM） c...Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode（DCM） controller and gate width controller,is proposed to improve efficiency.Instead of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike.The proposed converter has been designed and fabricated by a 0.35μm CMOS process.Measured results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.展开更多
A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficien...A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.展开更多
文摘设计了一种基于1 bit Sigma-Delta环路调制技术的高精度数字磁通门磁强计,建立了数字磁强计信号处理仿真模型,并利用Matlab的Simulink仿真工具开展了数字磁通门磁强计模型的仿真分析,对数字磁强计系统的噪声、线性度、响应速度和频率响应进行了仿真计算。利用本文1 bit Sigma-Delta环路调制技术的数字磁强计在量程超过±10^(5 )nT的情况下,系统在1 Hz处的噪声仅为4.66 pT·Hz^(-1/2),最大线性偏差为0.16 nT,动态响应速度达到2×10^(6) nT·s^(–1),频率响应带宽超过10 Hz。仿真结果表明,基于1 bit Sigma-Delta环路调制技术的数字磁通门磁强计可以有效降低对A/D转换器精度的要求,在保证性能的前提下大幅度降低了电路复杂程度,提高了系统的可靠性,在深空探测、空间磁场测量等领域具有广泛的应用前景。
基金supported by the National Natural Science Foundation of China(No.60576028)
文摘An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA011607)
文摘Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode（DCM） controller and gate width controller,is proposed to improve efficiency.Instead of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike.The proposed converter has been designed and fabricated by a 0.35μm CMOS process.Measured results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.
基金supported by the National High Technology Research and Development Program of China(No.2008AA010702)
文摘A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.
