A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is signif...A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Subject to specified power con- sumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator （VCO）, CP and phase/frequency detector （PFD） in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal （MOM） capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.展开更多
物联网(IoT)的飞速发展,使得远程抄表技术得到更进一步的发展。针对远程抄表这一问题,采用了蜂窝窄带物联网NB-IoT(Narrow Band Internet of Things)技术,解决远程抄表中吞吐率、广覆盖、低功耗、低成本、高可靠等实际问题,并对NB-IoT...物联网(IoT)的飞速发展,使得远程抄表技术得到更进一步的发展。针对远程抄表这一问题,采用了蜂窝窄带物联网NB-IoT(Narrow Band Internet of Things)技术,解决远程抄表中吞吐率、广覆盖、低功耗、低成本、高可靠等实际问题,并对NB-IoT模块进行射频测试与上位机软件设计。展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033)the National High-Tech Program of China(No.2013AA014103)
文摘A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Subject to specified power con- sumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator （VCO）, CP and phase/frequency detector （PFD） in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal （MOM） capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.
文摘物联网(IoT)的飞速发展,使得远程抄表技术得到更进一步的发展。针对远程抄表这一问题,采用了蜂窝窄带物联网NB-IoT(Narrow Band Internet of Things)技术,解决远程抄表中吞吐率、广覆盖、低功耗、低成本、高可靠等实际问题,并对NB-IoT模块进行射频测试与上位机软件设计。
