Self-heating and electric field distribution are the primary factors affecting the accuracy of the Ultra High Voltage Direct Current(UHVDC)resistive divider.Reducing the internal temperature rise of the voltage divide...Self-heating and electric field distribution are the primary factors affecting the accuracy of the Ultra High Voltage Direct Current(UHVDC)resistive divider.Reducing the internal temperature rise of the voltage divider caused by self-heating,reducing the maximum electric field strength of the voltage divider,and uniform electric field distribution can effectively improve the UHVDC resistive divider’s accuracy.In this paper,thermal analysis and electric field distribution optimization design of 1200 kV UHVDC resistive divider are carried out:(1)Using the proposed iterative algorithm,the heat dissipation and temperature distribution of the high voltage DC resistive divider are studied,and the influence of the ambient temperature and the power of the divider on the temperature of the insulating medium of the divider is analyzed;(2)Established the finite element models of 1200 kV and 2×600 kV DC resistive dividers,analyzed the influence of the size of the grading ring and the installation position on the maximum electric field strength of the voltage divider,and calculated the impact of the shielding resistor layer on the vicinity of the measuring resistor layer.The research indicates that:(1)The temperature of the insulating medium is linearly related to the horsepower of the voltage divider and the ambient temperature;(2)After the optimized design of the electric field,the maximum electric field strength of the 1200 kV DC resistive divider is reduced to 1471 V/mm,which is about 24% lower than that of the unoptimized design;(3)Installing the shielding resistor layer can significantly improve the electric field near the measuring resistor layer.This paper has an important reference function for improving the accuracy of the UHVDC resistive divider.展开更多
A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:...A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.展开更多
This paper presents fault detection,classification,and location for a PV-Wind-based DC ring microgrid in the MATLAB/SIMULINK platform.Initially,DC fault signals are collected from local measurements to examine the out...This paper presents fault detection,classification,and location for a PV-Wind-based DC ring microgrid in the MATLAB/SIMULINK platform.Initially,DC fault signals are collected from local measurements to examine the outcomes of the proposed system.Accurate detection is carried out for all faults,(i.e.,cable and arc faults)under two cases of fault resistance and distance variation,with the assistance of primary and secondary detection techniques,i.e.second-order differential current derivatived2I3 dt2and sliding mode window-based Pearson’s correlation coefficient.For fault classification a novel approach using modified multifractal detrended fluctuation analysis(M-MFDFA)is presented.The advantage of this method is its ability to estimate the local trends of any order polynomial function with the help of polynomial and trigonometric functions.It also doesn’t require any signal processing algorithm for decomposition resulting and this results in a reduction of computational burden.The detected fault signals are directly passed through the M-MFDFA classifier for fault type classification.To enhance the performance of the proposed classifier,statistical data is obtained from the M-MFDFA feature vectors,and the obtained data is plotted in 2-D and 3-D scatter plots for better visualization.Accurate fault distance estimation is carried out for all types of faults in the DC ring bus microgrid with the assistance of recursive least squares with a forgetting factor(FF-RLS).To verify the performance and superiority of the proposed classifier,it is compared with existing classifiers in terms of features,classification accuracy(CA),and relative computational time(RCT).展开更多
The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from volta...The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module （VRM） works in steady state, the ring-ADC＇s average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application.展开更多
为提高特高压直流换流阀塔绝缘可靠性、实现小安全裕度下换流阀绝缘的优化设计,以±1 100 k V直流换流阀作为研究对象,采用Solid Works及ANSYS混合建模技术,建立了换流阀塔的3维模型。对该模型进行单阀绝缘型式试验及多重阀直流耐...为提高特高压直流换流阀塔绝缘可靠性、实现小安全裕度下换流阀绝缘的优化设计,以±1 100 k V直流换流阀作为研究对象,采用Solid Works及ANSYS混合建模技术,建立了换流阀塔的3维模型。对该模型进行单阀绝缘型式试验及多重阀直流耐压试验,得到其电场分布;并针对电场薄弱环节进行局部结构优化。研究结果表明:当选取2 700 k V/m作为换流阀厅内金具表面工作控制电场强度时,单阀绝缘型式试验中的屏蔽罩及横梁均存在电场薄弱环节,有可能产生电晕及放电现象;而多重阀直流耐压试验中不存在电场薄弱环节,不会产生电晕及放电现象。此外,增加横梁拐角、屏蔽罩侧边的倒角值以及在层间绝缘金具处添加均压环可以使得薄弱处电场强度低于控制值。展开更多
基金supported by the Science and Technology Project of China Electric Power Research Institute,Research on 1200 kV DC Voltage Proportional Metering Technology with Weak Environmental Sensitivity and Development of Standard Devices(JL83-21-002).
文摘Self-heating and electric field distribution are the primary factors affecting the accuracy of the Ultra High Voltage Direct Current(UHVDC)resistive divider.Reducing the internal temperature rise of the voltage divider caused by self-heating,reducing the maximum electric field strength of the voltage divider,and uniform electric field distribution can effectively improve the UHVDC resistive divider’s accuracy.In this paper,thermal analysis and electric field distribution optimization design of 1200 kV UHVDC resistive divider are carried out:(1)Using the proposed iterative algorithm,the heat dissipation and temperature distribution of the high voltage DC resistive divider are studied,and the influence of the ambient temperature and the power of the divider on the temperature of the insulating medium of the divider is analyzed;(2)Established the finite element models of 1200 kV and 2×600 kV DC resistive dividers,analyzed the influence of the size of the grading ring and the installation position on the maximum electric field strength of the voltage divider,and calculated the impact of the shielding resistor layer on the vicinity of the measuring resistor layer.The research indicates that:(1)The temperature of the insulating medium is linearly related to the horsepower of the voltage divider and the ambient temperature;(2)After the optimized design of the electric field,the maximum electric field strength of the 1200 kV DC resistive divider is reduced to 1471 V/mm,which is about 24% lower than that of the unoptimized design;(3)Installing the shielding resistor layer can significantly improve the electric field near the measuring resistor layer.This paper has an important reference function for improving the accuracy of the UHVDC resistive divider.
基金Project supported by the Second Stage of Brain Korea 21
文摘A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.
文摘This paper presents fault detection,classification,and location for a PV-Wind-based DC ring microgrid in the MATLAB/SIMULINK platform.Initially,DC fault signals are collected from local measurements to examine the outcomes of the proposed system.Accurate detection is carried out for all faults,(i.e.,cable and arc faults)under two cases of fault resistance and distance variation,with the assistance of primary and secondary detection techniques,i.e.second-order differential current derivatived2I3 dt2and sliding mode window-based Pearson’s correlation coefficient.For fault classification a novel approach using modified multifractal detrended fluctuation analysis(M-MFDFA)is presented.The advantage of this method is its ability to estimate the local trends of any order polynomial function with the help of polynomial and trigonometric functions.It also doesn’t require any signal processing algorithm for decomposition resulting and this results in a reduction of computational burden.The detected fault signals are directly passed through the M-MFDFA classifier for fault type classification.To enhance the performance of the proposed classifier,statistical data is obtained from the M-MFDFA feature vectors,and the obtained data is plotted in 2-D and 3-D scatter plots for better visualization.Accurate fault distance estimation is carried out for all types of faults in the DC ring bus microgrid with the assistance of recursive least squares with a forgetting factor(FF-RLS).To verify the performance and superiority of the proposed classifier,it is compared with existing classifiers in terms of features,classification accuracy(CA),and relative computational time(RCT).
文摘The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module （VRM） works in steady state, the ring-ADC＇s average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application.
文摘为提高特高压直流换流阀塔绝缘可靠性、实现小安全裕度下换流阀绝缘的优化设计,以±1 100 k V直流换流阀作为研究对象,采用Solid Works及ANSYS混合建模技术,建立了换流阀塔的3维模型。对该模型进行单阀绝缘型式试验及多重阀直流耐压试验,得到其电场分布;并针对电场薄弱环节进行局部结构优化。研究结果表明:当选取2 700 k V/m作为换流阀厅内金具表面工作控制电场强度时,单阀绝缘型式试验中的屏蔽罩及横梁均存在电场薄弱环节,有可能产生电晕及放电现象;而多重阀直流耐压试验中不存在电场薄弱环节,不会产生电晕及放电现象。此外,增加横梁拐角、屏蔽罩侧边的倒角值以及在层间绝缘金具处添加均压环可以使得薄弱处电场强度低于控制值。
