A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay an...A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits. Keywords delay fault - false path - redundancy - stuck-at fault Regular PaperThis work was funded in part by Motorola India Electronics Ltd., Bangalore 560042, India.An earlier version of this paper appeared in the Proceedings of the 12th Int. Coaf. VLSI Design, Jan. 1999.Subhashis Majumder is a professor and course leader for the Computer Science and Engineering Department of International Institute of Information Technology, Kolkata. He started his career in Texas Instruments India Pvt. Ltd. and has over seven years of industry experience. He received his M. Tech degree in computer science from the Indian Statistical Institute, Kolkata in 1996. His undergraduate work was done in the Electronics and Telecommunication Engineering Dept. of the Jadvpur University, Koikata. He also worked as a research assistant in the Computer Eng. Dept. of Rutgers University for a year. He has led product development teams working on protocol stack development as well as VoIP. His current areas of interest include delay fault testing, wire routing, partitioning, approximation algorithms, and application of computational geometry to CAD problems.Bhargab B. Bhattacharya received the B.Sc. degree in physics from the Presidency College, Calcutta, the B.Tech. and M.Tech.展开更多
This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for tes...This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set;this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.展开更多
This paper presents a group-based dynamic stuck-at fault diagnosis scheme intended for resistive randomaccess memory(ReRAM).Traditional static random-access memory,dynamic random-access memory,NAND,and NOR flash memor...This paper presents a group-based dynamic stuck-at fault diagnosis scheme intended for resistive randomaccess memory(ReRAM).Traditional static random-access memory,dynamic random-access memory,NAND,and NOR flash memory are limited by their scalability,power,package density,and so forth.Next-generation memory types like ReRAMs are considered to have various advantages such as high package density,non-volatility,scalability,and low power consumption,but cell reliability has been a problem.Unreliable memory operation is caused by permanent stuck-at faults due to extensive use of write-or memory-intensive workloads.An increased number of stuck-at faults also prematurely limit chip lifetime.Therefore,a cellular automaton(CA)based dynamic stuck-at fault-tolerant design is proposed here to combat unreliable cell functioning and variable cell lifetime issues.A scalable,block-level fault diagnosis and recovery scheme is introduced to ensure readable data despite multi-bit stuck-at faults.The scheme is a novel approach because its goal is to remove all the restrictions on the number and nature of stuck-at faults in general fault conditions.The proposed scheme is based on Wolfram’s null boundary and periodic boundary CA theory.Various special classes of CAs are introduced for 100%fault tolerance:single-lengthcycle single-attractor cellular automata(SACAs),single-length-cycle two-attractor cellular automata(TACAs),and single-length-cycle multiple-attractor cellular automata(MACAs).The target micro-architectural unit is designed with optimal space overhead.展开更多
Modern VLSI circuits provide adequate on-chip resources. So that online testing and retry integrated into a chip are absolutely necessary for system-on-a-chip technology. This paper firstly proposes a general online t...Modern VLSI circuits provide adequate on-chip resources. So that online testing and retry integrated into a chip are absolutely necessary for system-on-a-chip technology. This paper firstly proposes a general online testing plus retrying structure. Obviously, although retry can mask transient or intermittent faults, it is useless for handling permanent faults generally. To solve this problem, this paper presents a novel dual modular redundancy （DMR） structure using complementary logic--alternating-complementary logic （CL-ACL） switching mode. During error-free operation, the CL-ACL structure operates by complementary logic mode. After an error is detected, it retries by alternating logic mode. If all errors belong to single or multiple temporary 0/1-error or stuck-at-error produced by one module, then these errors can be corrected effectively. The results obtained from the simulation validate the correctness of the CL-ACL structure. Analytic results show that the delay of the CL-ACL structure is dramatically less than that of a DMR structure using alternating-complementary logic mode.展开更多
文摘A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits. Keywords delay fault - false path - redundancy - stuck-at fault Regular PaperThis work was funded in part by Motorola India Electronics Ltd., Bangalore 560042, India.An earlier version of this paper appeared in the Proceedings of the 12th Int. Coaf. VLSI Design, Jan. 1999.Subhashis Majumder is a professor and course leader for the Computer Science and Engineering Department of International Institute of Information Technology, Kolkata. He started his career in Texas Instruments India Pvt. Ltd. and has over seven years of industry experience. He received his M. Tech degree in computer science from the Indian Statistical Institute, Kolkata in 1996. His undergraduate work was done in the Electronics and Telecommunication Engineering Dept. of the Jadvpur University, Koikata. He also worked as a research assistant in the Computer Eng. Dept. of Rutgers University for a year. He has led product development teams working on protocol stack development as well as VoIP. His current areas of interest include delay fault testing, wire routing, partitioning, approximation algorithms, and application of computational geometry to CAD problems.Bhargab B. Bhattacharya received the B.Sc. degree in physics from the Presidency College, Calcutta, the B.Tech. and M.Tech.
文摘This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set;this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.
文摘This paper presents a group-based dynamic stuck-at fault diagnosis scheme intended for resistive randomaccess memory(ReRAM).Traditional static random-access memory,dynamic random-access memory,NAND,and NOR flash memory are limited by their scalability,power,package density,and so forth.Next-generation memory types like ReRAMs are considered to have various advantages such as high package density,non-volatility,scalability,and low power consumption,but cell reliability has been a problem.Unreliable memory operation is caused by permanent stuck-at faults due to extensive use of write-or memory-intensive workloads.An increased number of stuck-at faults also prematurely limit chip lifetime.Therefore,a cellular automaton(CA)based dynamic stuck-at fault-tolerant design is proposed here to combat unreliable cell functioning and variable cell lifetime issues.A scalable,block-level fault diagnosis and recovery scheme is introduced to ensure readable data despite multi-bit stuck-at faults.The scheme is a novel approach because its goal is to remove all the restrictions on the number and nature of stuck-at faults in general fault conditions.The proposed scheme is based on Wolfram’s null boundary and periodic boundary CA theory.Various special classes of CAs are introduced for 100%fault tolerance:single-lengthcycle single-attractor cellular automata(SACAs),single-length-cycle two-attractor cellular automata(TACAs),and single-length-cycle multiple-attractor cellular automata(MACAs).The target micro-architectural unit is designed with optimal space overhead.
文摘Modern VLSI circuits provide adequate on-chip resources. So that online testing and retry integrated into a chip are absolutely necessary for system-on-a-chip technology. This paper firstly proposes a general online testing plus retrying structure. Obviously, although retry can mask transient or intermittent faults, it is useless for handling permanent faults generally. To solve this problem, this paper presents a novel dual modular redundancy （DMR） structure using complementary logic--alternating-complementary logic （CL-ACL） switching mode. During error-free operation, the CL-ACL structure operates by complementary logic mode. After an error is detected, it retries by alternating logic mode. If all errors belong to single or multiple temporary 0/1-error or stuck-at-error produced by one module, then these errors can be corrected effectively. The results obtained from the simulation validate the correctness of the CL-ACL structure. Analytic results show that the delay of the CL-ACL structure is dramatically less than that of a DMR structure using alternating-complementary logic mode.
