通过一则设计实例研究SOC(System On Chip)的可测性设计策略;15针对系统中的特殊模块采取专用的可测性策略,如对存储器进行内建自测试,对锁相环测试其性能参数等;其它模块采用基于ATPG(Automatic Test Pattern Generation)的结构化测试...通过一则设计实例研究SOC(System On Chip)的可测性设计策略;15针对系统中的特殊模块采取专用的可测性策略,如对存储器进行内建自测试,对锁相环测试其性能参数等;其它模块采用基于ATPG(Automatic Test Pattern Generation)的结构化测试方法进行测试,同时设计一些控制模块优化测试结构;经验证,应用这些策略,在满足了功耗和面积要求的前提下,系统总测试覆盖率达到了98.69%,且具有期望的可控制性和可观察性;因此在SOC设计中应灵活采用不同测试策略,合理分配测试资源从而达到预期的测试效果。展开更多
ATPG(automatic test pattern generation)是VLSI(very large scale integration circuits)电路测试中非常重要的技术,它的好坏直接影响测试成本与开销.然而现有的并行ATPG方法普遍存在负载不均衡、并行策略单一、存储开销大和数据局部...ATPG(automatic test pattern generation)是VLSI(very large scale integration circuits)电路测试中非常重要的技术,它的好坏直接影响测试成本与开销.然而现有的并行ATPG方法普遍存在负载不均衡、并行策略单一、存储开销大和数据局部性差等问题.由于图计算的高并行度和高扩展性等优点,快速、高效、低存储开销和高可扩展性的图计算系统可能是有效支持ATPG的重要工具,这将对减少测试成本显得尤为重要.本文将对图计算在组合ATPG中的应用进行探究;介绍图计算模型将ATPG算法转化为图算法的方法;分析现有图计算系统应用于ATPG面临的挑战;提出面向ATPG的单机图计算系统,并从基于传统架构的优化、新兴硬件的加速和基于新兴存储器件的优化几个方面,对图计算系统支持ATPG所面临的挑战和未来研究方向进行了讨论.展开更多
A simple,stable and reliable virtual logic analyzer is presented. The logic analyzer had two modules:one was the test pattern generation module,the other was the logic monitoring module. Combining the two modules,one ...A simple,stable and reliable virtual logic analyzer is presented. The logic analyzer had two modules:one was the test pattern generation module,the other was the logic monitoring module. Combining the two modules,one is able to test a digital circuit automatically. The user interface of the logic analyzer was programmed with LabVIEW. Two Arduino UNO boards were used as the hardware targets to input and output the logic signals. The maximum pattern update rate was set to be 20 Hz. The maximum logic sampling rate was set to be 200 Hz. After twelve thousand cycles of exhaustive tests,the logic analyzer had a 100% accuracy. As a tutorial showing how to build virtual instruments with Arduino,the software detail is also explained in this article.展开更多
文摘通过一则设计实例研究SOC(System On Chip)的可测性设计策略;15针对系统中的特殊模块采取专用的可测性策略,如对存储器进行内建自测试,对锁相环测试其性能参数等;其它模块采用基于ATPG(Automatic Test Pattern Generation)的结构化测试方法进行测试,同时设计一些控制模块优化测试结构;经验证,应用这些策略,在满足了功耗和面积要求的前提下,系统总测试覆盖率达到了98.69%,且具有期望的可控制性和可观察性;因此在SOC设计中应灵活采用不同测试策略,合理分配测试资源从而达到预期的测试效果。
文摘ATPG(automatic test pattern generation)是VLSI(very large scale integration circuits)电路测试中非常重要的技术,它的好坏直接影响测试成本与开销.然而现有的并行ATPG方法普遍存在负载不均衡、并行策略单一、存储开销大和数据局部性差等问题.由于图计算的高并行度和高扩展性等优点,快速、高效、低存储开销和高可扩展性的图计算系统可能是有效支持ATPG的重要工具,这将对减少测试成本显得尤为重要.本文将对图计算在组合ATPG中的应用进行探究;介绍图计算模型将ATPG算法转化为图算法的方法;分析现有图计算系统应用于ATPG面临的挑战;提出面向ATPG的单机图计算系统,并从基于传统架构的优化、新兴硬件的加速和基于新兴存储器件的优化几个方面,对图计算系统支持ATPG所面临的挑战和未来研究方向进行了讨论.
文摘A simple,stable and reliable virtual logic analyzer is presented. The logic analyzer had two modules:one was the test pattern generation module,the other was the logic monitoring module. Combining the two modules,one is able to test a digital circuit automatically. The user interface of the logic analyzer was programmed with LabVIEW. Two Arduino UNO boards were used as the hardware targets to input and output the logic signals. The maximum pattern update rate was set to be 20 Hz. The maximum logic sampling rate was set to be 200 Hz. After twelve thousand cycles of exhaustive tests,the logic analyzer had a 100% accuracy. As a tutorial showing how to build virtual instruments with Arduino,the software detail is also explained in this article.
基金supported by Hi-Tech Research and Development Program of China(2007AA01Z109)the National Natural Science Foundation of China(60633060)by the National Basic Research Program of China (973)(2005CB321604)
