摘要
本文对Verilog的语义级缺陷进行了研究,并提出了一种基于语义缺陷的自动化检测方法。通过对Verilog代码进行转换,得到两种包含不同语义信息的中间表达,并将其运用于语义级缺陷的自动检测方法。笔者们对Verilog设计中几种常见的语义级缺陷进行了说明与分析,并通过两种中间表达,从中提取了各种缺陷的特征。检测方法对转换后中间表达的语义信息进行提取,与缺陷的特征进行比较,从而实现对缺陷的检测。经实际应用,该方法满足了可编程逻辑器件的测试工作需求,提升了静态测试工作的分析效率与准确率。
This article carries out research on semantic-level defects of Verilog, and presents a semantic-based defect auto-analysis method. Two Intermediate Expressions (IRs) which contain different semantic-level information can be generated by converting Verilog code. The authors demonstrate and analyze several common defects in Verilog designs, and extract the characteristics of various defects through two Intermediate Expressions. The detection method extracts the semantic information of the intermediate expression after transformation and compares it with the feature of the defect, so as to realize the detection of the defect. Through practical application, this method can satisfy the requirement of programmable logic device testing and improve the analysis efficiency and accuracy of static testing.
出处
《计算机科学与应用》
2022年第11期2442-2450,共9页
Computer Science and Application
