摘要
描述了一种高性能CMOS线阵 2 88× 4读出电路的设计。该读出电路是一个大规模混合信号电路 ,集成了时间延迟积分以提高信噪比 ,实现了缺陷像素剔除以提高阵列的可靠性。其他特征包括积分时间可调 ,多级增益 ,双向扫描 ,超采样 ,以及内建电测试。该芯片采用 1 2 μm双层多晶硅双层金属CMOS工艺。测量得到的总功耗约为 2 4mW ,工作电压 5V。
A high performance CMOS linear 288×4 readout integrated circuit (ROIC) is detailed in this paper. It is a large-scale mixed-signal circuit with time-delay integration (TDI) function to enhance the signal to noise ratio (S/N), and defective element deselection (DED) function to decrease the probability of bad columns. The other features include adjustable integration time, multi gain, bi-direction of TDI scan, super-sample, and electrical test. Digital I/O ports are designed to control its work mode. It is fabricated using 1.2?μm double poly double metal (DPDM) CMOS technology. The measured power consume is about 24?mW at 5?V supply.
出处
《北京大学学报（自然科学版）》
CAS
CSCD
北大核心
2004年第3期402-406,共5页
Acta Scientiarum Naturalium Universitatis Pekinensis
基金
电子预先研究基金资助项目 (413 0 80 2 0 10 2 )
