摘要
研究分析了CMOS多晶电容的工艺误差,给出了氧化硅介质层厚度的梯度误差、边际效应等工艺因素对CMOS多晶电容的影响。基于单位电容的改进设计,给出了CMOS多晶电容阵列的共心设计方法。采用0.6μmCMOS DPDM工艺,实现了基于CMOS多晶电容阵列的开关电容带通滤波器,实验结果表明本文的CMOS多晶电容设计方法具有较高的精度,能直接用于亚微米及深亚微米集成电路设计。
The technology errors of CMOS poly-silicon capacitor are analyzed. The effect of various errors introduced during fabrication on CMOS poly-silicon capacitor is discussed. Based on the improved design of unit-capacitors, the common-centroid floorplan of poly-silicon capacitor is presented. On the proposed capacitor design way, the CMOS switch-capacitor bandpass filters is implemented using 0.6μm CMOS DPDM process. The measured results of filters show that the proposed capacitor design way can be used to design high accuracy capacitors, and applied to the design of sub-micro and deep sub-micro analog integrated circuit.
出处
《电子器件》
CAS
2004年第1期24-26,共3页
Chinese Journal of Electron Devices
基金
国家高技术研究发展863计划资助项目(2002AA1Z1210)
关键词
多晶电容
CMOS
工艺误差
共心分布
Poly-silicon capacitor
CMOS
Technology Errors
Common-center floorplan
