摘要
给出了基于 0 2 μm砷化镓赝晶高电子迁移率器件工艺设计的高速锁相环芯片的电路结构、性能分析与测试结果 .芯片采用吉尔伯特结构的鉴相器和交叉耦合负阻差分环形压控振荡器 ,总面积为 1 1 5mm× 0 75mm .锁定时中心工作频率为 4 44GHz ,锁定范围约为 360MHz,在1 0 0kHz频偏处的单边带相位噪声约 - 1 0 7dBc/Hz,经适当修改后可应用于光纤通信系统中的时钟数据恢复电路 .
A 5 GHz phase-locked loop (PLL) chip based on 0.2 μm GaAs PHEMT (pseudomorphic high-electron-mobility transistor) technology has been realized and characterized. The chip size is 1.15 mm × 0.75 mm with a phase detector using Gilbert cell and a differential ring voltage controlled oscillator (VCO) using cross-coupled negative resistance. The locking range is approximately 360 MHz with a center frequency of 4.44 GHz and the phase noise is -107 dBc/Hz at 100 kHz offset. The PLL chip can be adopted in the clock and data recovery circuits of the optic-fiber communication systems after appropriate modification.
出处
《东南大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2004年第2期157-160,共4页
Journal of Southeast University：Natural Science Edition
基金
国家 8 63计划资助项目 ( 2 0 0 1AA3 12 0 60 )
