摘要
针对LDPC码译码算法硬件实现复杂度高和开发周期长的问题,提出了采用一种高层次综合的方式来高效地实现硬件设计.以实现码率兼容QC-LDPC码的最小和译码算法的硬件实现为目的,首先使用C语言对该算法结构进行描述,再对数据存储和循环调度等方面进行调整和优化以适应硬件环境.然后利用高层次综合工具在接口综合、循环优化、数组优化等方面进一步优化,提高译码模块的资源利用率和数据吞吐率.最后通过C综合实现算法的RTL级描述.联合仿真结果表明,用高层次综合工具实现LDPC译码器在大大缩短开发周期的前提下,仍然具有优异的译码性能.
Aiming at the problem of high complexity and long development cycle of Low-Density Parity-Check(LDPC)code decoding algorithm,a high-level synthesis method is proposed to realize the hardware design effectively.The purpose of this paper is to realize the hardware implementation of code-rate-compatible QC-LDPC decoding algorithm.Firstly,the structure of the algorithm is described by using C language.Secondly,the algorithm is adjusted and optimized from the data storage and cyclic scheduling in the code to adapt to the hardware surroundings.And then use the high-level synthesis tool to further constrain the algorithm behavior in interface synthesis,loop optimization,array optimization and so on,and improve the resource utilization rate and data throughput rate of the decoding module.Finally,through the RTL level description of C integrated algorithm,a variety of optimization schemes are comparatively analyzed to deeply understand the high-level comprehensive implementation details of LDPC code decoding algorithm.The results of co-simulation show that using high-level synthesis tools to achieve LDPC decoder in the greatly shorten the development cycle,still has better decoding performance.
作者
张志芳
朱鹏景
朱铁林
赵旦峰
ZHANG Zhi-fang;ZHU Peng-jing;ZHU Tie-lin;ZHAO Dan-feng(Tianjin Zhongwei Aerospace Data System Technology Co.,Ltd.,Tianjin 300458,China;Information and Communication Engineering,Harbin Engineering University,Harbin 150001,China)
出处
《微电子学与计算机》
北大核心
2019年第5期53-57,共5页
Microelectronics & Computer
基金
国家重点研发计划地球观测与导航重点专项(2016YFB0502602)
