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应用于10bit 10MSPS SAR ADC的自举采样开关的设计 被引量:1

Design of a Bootstrapped Sampling Switch Applied for 10 Bit 10MSPS SAR ADC
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摘要 基于Global Foundries 0.18μm CMOS工艺,设计了一种用于10bit 10MSPS SAR ADC的栅压自举采样开关电路.讨论了互补型CMOS采样开关和传统的栅压自举采样开关的不足,提出了一种新型的栅压自举采样开关电路结构,有效地提高了该电路的可靠性.仿真结果表明:当输入信号频率接近奈奎斯特频率时,该栅压自举采样开关电路的信噪比可以达到72dB,可以适用于10bit 10MSPS SAR ADC的应用需求. A bootstrapped sampling switch applied for 10 bits 10MSPS SAR ADC is designed based on the Global Foundries 0.18μm CMOS process.The disadvantages of complemented CMOS sampling switch and conventional bootstrapped sampling switch are discussed.A new bootstrapped sampling circuit topology is presented to efficiently achieve high reliability.Simulation result shows that the SNDR of the proposed circuit can reach 72 dB when input signal frequency closes to Nyquist frequency,which satisfies the requirement of 10 bits 10MSPS SAR ADC.
出处 《微电子学与计算机》 CSCD 北大核心 2014年第11期102-105,110,共5页 Microelectronics & Computer
基金 国家"九七三"计划(2011CB808003) 福建省自然科学基金(2012J01269)
关键词 采样开关 SAR 栅压自举开关 sampling switch SAR Bootstrapped switch
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  • 1骆冬根,黄鲁,胡新伟.一种模数转换器的采样保持/增益减法电路设计[J].微电子学与计算机,2005,22(10):54-57. 被引量:3
  • 2Wenhua Y D K. A 3 - V 340 - mW 14 - b 75 - Msample/ s CMOS AIX; With 85 -dB SFDR at Nyquist Input[J]. IEEE Journal of Solid - State Circuits, 2001, 36 (12) : 1931 - 1936. 被引量:1
  • 3Klass B, Govert G. A fast settling CMOS opamp for SC circuits with 90 dB DC gain [ J ]. IEEE Journal of Solid State Circuits, 1990, 25(6) : 1379 - 1384. 被引量:1
  • 4Miyazaki D, Furuta M, Kawahito S. A 16roW 30MSample/s 10b pipelined A/D oonverter using a pseudo differential architecture[ R]. Solid - State Circuits Conference ISSOC IEEE International, 2002:134 - 135. 被引量:1
  • 5Abo A M. Design for reliability of lowvoltage, switched capacitor circuits [ D]. Berkeley: University of California, PHD Thesis, 1999. 被引量:1
  • 6Allen P E, Holberg D R. CMOS analog circuit design[M].2nd ed.北京:电子工业出版社,2005. 被引量:1
  • 7Abo A M, Gray P R. A 1.5V 10bit 14.3MS/s CMOS pipeline analog- to- digital converter[J ]. IEEE J Sol Sta Circ, 1999, 34(5) : 599 - 606. 被引量:1
  • 8Chouia Y, El- Sankary K, Saleh A, et al. 14 b, 50 MS/s CMOS front- end sample and hold module dedieated to a pipelined ADC[C]//The 47th IEEE Int Midwest Symp Cite and Syst. Hiroshima, Japa, 2004 : 353 - 356. 被引量:1
  • 9Maloberti F, Franeeseoni F, Maleovati P, et al. Design considerations on low voltage low power data converters [J]. IEEE Trans Circ and Syst I, 1995, 42(11):653- 863. 被引量:1
  • 10Steensgaard J. Bootstrapped low voltage analog switches [C]// IEEE lnt Symp Circ and Syst. USA, Orlando,1999:29 -32. 被引量:1

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