摘要
静态时序分析由于速度快和容量大而广泛应用于时序验证,而门延时的计算则是静态时序分析中的关键部分。以前利用等效输出驱动点导纳函数相等原理产生的模型,由于不能很好的与等效电容公式结合,门延时的计算存在过于悲观性或乐观性结果。本文采用输出驱动导纳和互连线拓扑结构相结合的方法, 对门延时负载模型进行了改进,很好地与等效电容计算结合,保证了静态时序分析的准确性。
Static timing analysis is widely applied in timing verification because of its high speedand great capacity. The gate delay computing is a critical part of static timing analysis. The old gatedelay models utilizing the theory that equivalent output driving point admittance formulation isequal can’t combine with equivalent capacitance formulation very well, which results in the toopessimistic or optimistic gate delay. This paper takes output driving point admittance and intercon-nect structure into account in calculating the equivalent capacitance of the driver, which guaranteesthe accuracy of static timing analysis.
出处
《半导体技术》
CAS
CSCD
北大核心
2003年第7期43-46,共4页
Semiconductor Technology
基金
国家重点基础研究发展规划(G1999022903)
国家自然科学杰出青年基金(60025101)
"863"计划(2002AA1Z1460)项目。
