摘要
以集成电路的快速发展与广泛应用为契机,针对FPGA开发过程中IP软核可复用的特点,提出一种提升FPGA嵌入式块存储器工作频率的IP软核设计方法。利用软件对不同读写类型和不同输入位宽的数据进行预处理,获取所需的硬件资源开销,并生成相应的硬件描述语言。IP软核设计时,在使用固定硬件资源的情况下,通过优化数据预处理方法,以及改变在综合阶段布局布线的处理结果,提高了工作频率。对设计的IP软核进行测试验证,结果表明,该设计方法生成的IP软核的功能和性能指标均符合设计要求,其工作频率最高可提升25.56%。
With the rapid development and wide application of integrated circuits,a new IP soft core design method was proposed to improve the frequency of embedded block RAM in FPGA,which was based on the reusability of IP soft core.The data with different type of read/write and different input bit width were pretreated by software to obtain the required hardware resource cost,so the corresponding hardware description language was generated.In the design,the working frequency was improved in limited hardware resources through optimizing the data preprocessing method and changing the result of layout in the synthesis stage.The designed IP soft core had been verified by functional simulation.Experimental results showed that the proposed design method could meet the functional and performance requirements,and the maximum working frequency could be increased by 25.56%.
作者
许莉
韦嵚
车书玲
XU Li;WEI Qin;CHE Shuling(State Key Laboratory of Integrated Service Networks,Xidian University,Xi’an710000,P.R.China;Xi’an Intelligence Silicon Technology Co.,Ltd.,Xi’an710000,P.R.China)
出处
《微电子学》
CAS
北大核心
2019年第4期524-528,共5页
Microelectronics
关键词
FPGA
嵌入式块存储器
IP软核
高速
field programmable gate array
embedded block RAM
IP soft core
high speed
